Electrical transceiver for synchronous ethernet
First Claim
1. A method of synchronous Ethernet communications to be implemented in an electrical transceiver including a first interface coupled to a host device and a second interface including a physical layer transceiver coupled to a serial link, the method comprising:
- frequency synchronizing, in a physical layer of the electrical transceiver, without using a higher layer protocol, a first signal received from the second interface to a frequency extracted from a second signal that is received from the first interface, so as to make a time delay of the first signal equal to a time delay of the second signal,wherein the frequency synchronizing comprises controlling the first signal and the second signal through a first buffer and a second buffer of a delay equalizer such that the first signal and the second signal have a same time delay, by controlling buffering speeds of the first buffer and the second buffer based on a delay difference.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.
16 Citations
11 Claims
-
1. A method of synchronous Ethernet communications to be implemented in an electrical transceiver including a first interface coupled to a host device and a second interface including a physical layer transceiver coupled to a serial link, the method comprising:
-
frequency synchronizing, in a physical layer of the electrical transceiver, without using a higher layer protocol, a first signal received from the second interface to a frequency extracted from a second signal that is received from the first interface, so as to make a time delay of the first signal equal to a time delay of the second signal, wherein the frequency synchronizing comprises controlling the first signal and the second signal through a first buffer and a second buffer of a delay equalizer such that the first signal and the second signal have a same time delay, by controlling buffering speeds of the first buffer and the second buffer based on a delay difference. - View Dependent Claims (7, 8, 9)
-
-
2. A method of providing a time of day synchronization without asymmetry to be implemented in an electrical transceiver including a first interface coupled to a host device and a second interface including a physical layer transceiver coupled to a serial link, the method comprising:
-
reducing asymmetry for precision time protocol (PTP) or network timing protocol (NTP) traffic, in a physical layer of the electrical transceiver, without using a higher layer protocol, by making packet latency paths in both directions equal to each other between the first interface and the second interface, wherein the reducing asymmetry comprises controlling a first signal received from the first interface and a second signal received from the second interface, through a first buffer and a second buffer of a delay equalizer such that the first signal and the second signal have a same time delay, by controlling buffering speeds of the first buffer and the second buffer based on a delay difference. - View Dependent Claims (3, 10, 11)
-
-
4. A method of providing a time of day synchronization without packet delay variation (PDV) to be implemented in an electrical transceiver including a first interface coupled to a host device and a second interface including a physical layer transceiver coupled to a serial link, the method comprising:
-
providing a fixed delay for all traffic including precision time protocol (PTP) or network time protocol (NTP) traffic, in a physical layer of the electrical transceiver, without using a higher layer protocol, by making delays of paths in both directions equal to each other between the first interface and the second interface, wherein the delays of paths in both direction are made equal to each other by controlling the first signal and the second signal through a first buffer and a second buffer of a delay equalizer, and buffering speeds of the first buffer and the second buffer are controlled based on a delay difference. - View Dependent Claims (5, 6)
-
Specification