Solid-state imaging apparatus and imaging with a limiting circuit for limiting an amplifier output in first and second periods to first and second ranges

• US 9,942,497 B2
• Filed: 03/27/2014
• Issued: 04/10/2018
• Est. Priority Date: 04/18/2013
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Ikeda, Yasuji, Hiyama, Hiroki
• Primary Examiner(s): Le, Que T
• Assistant Examiner(s): BENNETT, JENNIFER D
• Application Number:
  US14/226,996
• Publication Number:
  US 20140312207A1
• Time in Patent Office: 1,475 Days
• Field of Search: 2502081, 250214 A, 250214 R, 3482291, 348294, 348297, 348300, 348302, 348308, 257257, 257258, 257290, 257291, 257292
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/627 Detection or reduction of inverted contrast or eclipsing effects
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A solid-state imaging apparatus and an imaging system which can reduce the occurrence of darkening and decrease deterioration in CDS performance are provided. The solid-state imaging apparatus has: a pixel unit including a photoelectric conversion unit for generating a signal by a photoelectric conversion; an amplifier unit for amplifying the signal generated by the photoelectric conversion unit; and a limiting circuit for limiting a level of an output signal from the amplifier unit. The pixel unit outputs a noise signal under a reset state during a first period and outputs a pixel signal under a non-reset state during a second period. The limiting circuit limits the level of the output signal from the amplifier unit in the first period, lower than the level of the output signal from the amplifier unit in the second period.

Claims

1. A solid-state imaging apparatus comprising:

a pixel unit including a photoelectric conversion unit configured to generate a first signal by a photoelectric conversion and a pixel amplification unit configured to input the first signal and to output a second signal onto an output line;

an amplifier unit, connected to the output line, configured to amplify the second signal output onto the output line by the pixel unit; and

a limiting circuit configured to limit a level of an output signal from the amplifier unit, wherein

as the second signal, the pixel unit outputs a noise signal under a reset state during a first period and outputs a pixel signal under a non-reset state during a second period,

the limiting circuit limits the level of the output signal from the amplifier unit in the first period to a first range, and limits the level of the output signal from the amplifier unit in the second period to a second range, the first range being narrower than the second range, and

the limiting circuit is switched from the first range to the second range before the second period,

the amplifier unit has a differential amplifier having a first input node and a second input node,

the pixel signal from the pixel unit is input to the first input node, and a reference voltage is input to the second input node, and

the first range is determined based on the reference voltage and an offset voltage of the differential amplifier.

2. The solid-state imaging apparatus according to claim 1, wherein the amplifier unit has a differential amplifier circuit,

the differential amplifier circuit has a differential pair and a constant current circuit, and

the limiting circuit is provided between an output node of the differential amplifier circuit and the constant current circuit.

3. The solid-state imaging apparatus according to claim 1, wherein the amplifier unit has a folded cascode amplifier circuit,

the folded cascode amplifier circuit has a constant current circuit, a differential input pair and a differential pair connected in a cascode, and

the limiting circuit is provided between the constant current circuit and an output node of the differential pair connected in the cascode.

4. The solid-state imaging apparatus according to claim 1, wherein the amplifier unit has a differential amplifier circuit and a buffer circuit connected to a following stage of the differential amplifier circuit,

the differential amplifier circuit has a constant current circuit and a differential pair, and

the limiting circuit is provided between the constant current circuit and an output node of the differential amplifier circuit.

5. The solid-state imaging apparatus according to claim 1, wherein the amplifier unit has a differential amplifier circuit and a buffer circuit connected to a following stage of the differential amplifier circuit,

the differential amplifier circuit has a constant current circuit and a differential pair, and

the limiting circuit is provided between an output node of the buffer circuit and a node of a ground potential.

6. The solid-state imaging apparatus according to claim 4, wherein the buffer circuit is a common source amplifier circuit.

7. The solid-state imaging apparatus according to claim 1, further comprising an analog to digital converter configured to convert an analog signal amplified by the amplifier unit to a digital signal.

8. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit is a MOS transistor, configured to limit the level of the output signal from the amplifier unit by flowing a current into the MOS transistor.

9. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit is provided in a feedback loop of the amplifier unit.

10. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit is provided out of a feedback loop of the amplifier unit, and at an output node of the amplifier unit.

11. An imaging system comprising the solid-state imaging apparatus according to claim 1;

and

an optical system configured to focus light onto the solid-state imaging apparatus.

12. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit is a MOS transistor, a voltage supplied to a gate of the MOS transistor is switched between the first period and the second period, such that a range to which the level of the output signal from the amplifier unit is limited is changed between the first period and the second period.

13. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit is a MOS transistor, a voltage supplied to a gate of the MOS transistor is switched between the first period and the second period, such that the limiting circuit limits the level of the output signal from the amplifier unit in the first period to a first range, and limits the level of the output signal from the amplifier unit in the second period to a second range, the first range being narrower than the second range.

14. The solid-state imaging apparatus according to claim 1, wherein the amplifier unit clamps the signal generated by the photoelectric conversion unit during a clamping period, and

the limiting circuit is switched from the first range to the second range after the clamping period and before the second period.

15. The solid-state imaging apparatus according to claim 1, wherein the limiting circuit includes a MOS transistor whose gate inputs a clip voltage (VCLIP_N) that is equal to a voltage (VREF+VOD+Δ

Vth), where VREF is the reference voltage, Δ

Vth is a maximum variation of offset voltage of the differential amplifier, and VOD is an overdrive voltage of the MOS transistor.