LDO regulator with improved load transient performance for internal power supply

• US 9,946,282 B2
• Filed: 08/23/2016
• Issued: 04/17/2018
• Est. Priority Date: 01/02/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Shenzhen R&D Co Ltd (STMicroelectronics NV)
• Inventors: Liu, Yong Feng
• Primary Examiner(s): Torres-Rivera, Alex
• Application Number:
  US15/244,289
• Publication Number:
  US 20160357206A1
• Time in Patent Office: 602 Days
• Field of Search: 323273
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G05F 1/59 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

Claims

1. A circuit, comprising:

a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node; and

a transient recovery circuit, comprising;

a first transistor having a first source-drain path coupled to a control terminal of the drive transistor;

a first control circuit configured to deactuate the first transistor when the voltage regulator circuit is operating in a quiescent state and actuate the first transistor in response to detection of a transient voltage drop at the regulated output node to source a first current to the control terminal of the drive transistor in addition to a regulation control current applied by the feedback regulation loop;

a second transistor having a second source-drain path coupled to the regulated output node; and

a second control circuit configured to bias operation of the second transistor to sink a first non-zero magnitude current from the regulated output node when the voltage regulator circuit is operating in the quiescent state and to bias operation of the second transistor to sink a second non-zero magnitude current that is greater than the first non-zero magnitude current from the regulated output node in response to detection of a transient voltage increase at the regulated output node.

2. The circuit of claim 1, wherein said first control circuit is configured to source a biasing current to the regulated output node when the voltage regulator circuit is operating in the quiescent state, and wherein said first non-zero magnitude current offsets said biasing current.

3. The circuit of claim 2, wherein the first control circuit comprises:

a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent state;

a current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output said bias current; and

a resistor configured to receive the bias current and generate a bias voltage applied to a control terminal of the first transistor.

4. The circuit of claim 3, wherein the bias current is a fraction of the input current.

5. The circuit of claim 3, wherein the bias current has a magnitude sufficient to cause the resistor to generate the bias voltage in the quiescent state which is less than a threshold turn on voltage of the first transistor.

6. The circuit of claim 5, wherein the current mirror circuit is configured to respond to the transient voltage drop by increasing the bias current to a magnitude sufficient to cause the resistor to generate the bias voltage in excess of the threshold turn on voltage of the first transistor.

7. The circuit of claim 3, wherein the input current is supplied from a regulated reference current.

8. The circuit of claim 1, wherein the second control circuit comprises:

a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent state;

a current mirror circuit including the second transistor, said current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror circuit configured to receive an input current and output the second current; and

a capacitor coupled to a common control terminal of the current mirror circuit and configured to apply a fixed bias voltage to a control terminal of the second transistor.

9. The circuit of claim 8, wherein the second current is a fraction of the input current.

10. The circuit of claim 8, wherein the current mirror circuit is configured to respond to the transient voltage increase by increasing the magnitude of the second current.

11. The circuit of claim 1, wherein said transient recovery circuit further comprises:

a third transistor having a third source-drain path coupled to a control terminal of the drive transistor; and

a third control circuit configured to deactuate the third transistor when the voltage regulator circuit is operating in the quiescent state and actuate the third transistor in response to detection of the transient voltage increase to sink a third current from the control terminal of the drive transistor in addition to the regulation control current and first current.

12. A method, comprising:

operating a drive transistor of a voltage regulator circuit to source current to a regulated output node using a feedback regulation loop;

in response to a sensed transient voltage decrease at the regulated output node, sourcing current into a control terminal of the drive transistor in addition to current sourced to the control terminal by operation of the feedback regulation loop;

sinking a first non-zero magnitude current from the regulated output node when the voltage regulator circuit is operating in a quiescent state; and

in response to a sensed transient voltage increase at the regulated output node, sinking a second non-zero magnitude current that is greater than the first non-zero magnitude current from the regulated output node.

13. The method of claim 12, further comprising not sourcing current into the control terminal of the drive transistor when the voltage regulator circuit is operating in the quiescent state.

14. The method of claim 12, further comprising in response to a sensed transient voltage increase at the regulated output node sinking current from the control terminal of the drive transistor in addition to current sourced to the control terminal by operation of the feedback regulation loop.

15. A circuit, comprising:

a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node;

a first transistor having a first source-drain path coupled to the regulated output node and configured to source a first current to said regulated output node when the voltage regulator circuit is operating in a quiescent state;

a second transistor having a second source-drain path coupled to the regulated output node; and

a control circuit configured to bias operation of the second transistor to sink a first non-zero magnitude current from the regulated output node when the voltage regulator circuit is operating in the quiescent state and to bias operation of the second transistor to sink a second, greater, non-zero magnitude current from the regulated output node in response to detection of a transient voltage increase at the regulated output node;

wherein the first non-zero magnitude current sunk from the regulated output node offsets the first current sourced to the regulated output node.

16. A circuit, comprising:

a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node;

a first transistor having a first source-drain path coupled to the regulated output node and configured to source a first current to said regulated output node when the voltage regulator circuit is operating in a quiescent state;

a second transistor having a second source-drain path coupled to the regulated output node;

a control circuit configured to bias operation of the second transistor to sink a first non-zero magnitude current from the regulated output node when the voltage regulator circuit is operating in the quiescent state and to bias operation of the second transistor to sink a second, greater, non-zero magnitude current from the regulated output node in response to detection of a transient voltage increase at the regulated output node; and

a third transistor having a third source-drain path coupled to a control terminal of the drive transistor, wherein said first transistor is configured to bias said third transistor in an off state when the voltage regulator circuit is operating in a quiescent state.

17. The circuit of claim 16, wherein said first transistor responds to detection of a transient voltage decrease at the regulated output node to switch said third transistor to an on state.

18. A circuit, comprising:

a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to an output node; and

a transient recovery circuit, comprising;

a first transistor having a first source-drain path coupled to a control terminal of the drive transistor;

a first control circuit configured to deactuate the first transistor when a voltage at the output node is regulated to a regulated voltage level set by the feedback regulation loop and actuate the first transistor to source a first current to the control terminal of the drive transistor in response to the voltage at the output node experiencing a transient voltage drop;

a second transistor having a second source-drain path coupled to the regulated output node; and

a second control circuit configured to bias operation of the second transistor to sink a first non-zero magnitude current from the regulated output node when the voltage at the output node is regulated to the regulated voltage level set by the feedback regulation loop and to bias operation of the second transistor to sink a second non-zero magnitude current greater than the first non-zero magnitude current from the regulated output node in response to the voltage at the output node experiencing a transient voltage increase.

19. The circuit of claim 18, wherein said first control circuit is configured to source a biasing current to the regulated output node when the voltage at the output node is regulated to the regulated voltage level set by the feedback regulation loop, and wherein said first non-zero magnitude current offsets said biasing current.

20. The circuit of claim 19, wherein the first control circuit comprises:

a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the regulating mode;

a current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output said bias current; and

a resistor configured to receive the bias current and generate a bias voltage applied to a control terminal of the first transistor.

21. The circuit of claim 20, wherein the bias current is a fraction of the input current.

22. The circuit of claim 20, wherein the bias current has a magnitude sufficient to cause the resistor to generate the bias voltage in the regulating mode which is less than a threshold turn on voltage of the first transistor.

23. The circuit of claim 22, wherein the current mirror circuit is configured to respond to the transient voltage drop by increasing the bias current to a magnitude sufficient to cause the resistor to generate the bias voltage in excess of the threshold turn on voltage of the first transistor.

24. The circuit of claim 20, wherein the input current is supplied from a regulated reference current.

25. The circuit of claim 18, wherein the second control circuit comprises:

a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the regulating mode;

a current mirror circuit including the second transistor, said current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror circuit configured to receive an input current and output the second current; and

a capacitor coupled to a common control terminal of the current mirror circuit and configured to apply a fixed bias voltage to a control terminal of the second transistor.

26. The circuit of claim 25, wherein the second current is a fraction of the input current.

27. The circuit of claim 25, wherein the current mirror circuit is configured to respond to the transient voltage increase by increasing the magnitude of the second current.

28. The circuit of claim 18, wherein said transient recovery circuit further comprises:

a third transistor having a third source-drain path coupled to a control terminal of the drive transistor; and

a third control circuit configured to deactuate the third transistor when the voltage at the output node is regulated to the regulated voltage level set by the feedback regulation loop and actuate the third transistor to sink a third current from the control terminal of the drive transistor to the voltage at the output node is experiencing the transient voltage increase.

29. A circuit, comprising:

a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to an output node to generate a voltage at the output node that is regulated to a regulated voltage level set by the feedback regulation loop;

a first transistor having a first source-drain path coupled to the regulated output node and configured to source a first current to said regulated output node;

a second transistor having a second source-drain path coupled to the regulated output node; and

a control circuit configured to bias operation of the second transistor to sink a first non-zero magnitude current from the regulated output node when the voltage at the output node is regulated to the regulated voltage level set by the feedback regulation loop and to bias operation of the second transistor to sink a second non-zero magnitude current greater than the first non-zero magnitude current from the regulated output node in response to the voltage at the output node experiencing a transient voltage increase.

30. The circuit of claim 29, wherein the first non-zero magnitude current sunk from the regulated output node offsets the first current sourced to the regulated output node.

31. The circuit of claim 29, further comprising a third transistor having a third source-drain path coupled to a control terminal of the drive transistor, wherein said first transistor is configured to bias said third transistor in an off state when the voltage at the output node is regulated to the regulated voltage level set by the feedback regulation loop.

32. The circuit of claim 31, wherein said first transistor is further configured to switch said third transistor to an on state in response to the voltage at the output node experiencing a transient voltage decrease.

33. A method, comprising:

operating a drive transistor of a voltage regulator circuit to source current to a regulated output node using a feedback regulation loop to generate a regulated voltage at the regulated output node during a regulating mode of operation;

in response to a sensed transient voltage decrease at the regulated output node, sourcing current into a control terminal of the drive transistor in addition to current sourced during a transient mode of operation to the control terminal by operation of the feedback regulation loop;

sinking a first non-zero magnitude current from the regulated output node when the voltage regulator circuit is operating in the regulating mode of operation; and

in response to a sensed transient voltage increase at the regulated output node, sinking a second, greater, non-zero magnitude current from the regulated output node during the transient mode of operation.

34. The method of claim 33, further comprising not sourcing current into the control terminal of the drive transistor when the voltage regulator circuit is operating in the transient mode of operation.

35. The method of claim 33, further comprising in response to a sensed transient voltage increase at the regulated output node sinking current from the control terminal of the drive transistor during the transient mode of operation in addition to current sourced to the control terminal by operation of the feedback regulation loop.