Method and structure for mandrel and spacer patterning

• US 9,946,827 B2
• Filed: 07/16/2015
• Issued: 04/17/2018
• Est. Priority Date: 07/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chung-Ming, Peng, Chih-Hsiung, Chang, Chi-Kang, Chen, Kuei-Shun, Fu, Shih-Chi
• Primary Examiner(s): AISAKA, BRYCE M
• Application Number:
  US14/801,383
• Publication Number:
  US 20170017745A1
• Time in Patent Office: 1,006 Days
• Field of Search: 716119
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region

Abstract

A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

Claims

1. A method, comprising:

receiving an integrated circuit (IC) design layout, wherein the IC design layout includes a first layout block and a second layout block, the first layout block includes a first line pattern oriented lengthwise in a first direction, the second layout block includes a second line pattern oriented lengthwise in the first direction, and the first and second layout blocks are separated by a first space, wherein the first and second line patterns are physically separate from each other;

adding a dummy pattern to the first space so that the first and second line patterns become physically connected through the dummy pattern, wherein the dummy pattern is designed to be transferred onto a wafer;

outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format, wherein the mandrel pattern layout includes the first and second line patterns and the dummy pattern, and wherein the cut pattern layout includes a pattern corresponding to the first space;

manufacturing a first mask with the mandrel pattern layout; and

manufacturing a second mask with the cut pattern layout.

2. The method of claim 1, further comprising:

performing a first patterning process to a substrate with the first mask, thereby forming one or more features on the substrate; and

performing a second patterning process to the substrate with the second mask, thereby removing a first portion of the one or more features, wherein the first portion lies in a region corresponding to the first space in the IC design layout.

3. The method of claim 2, wherein the first patterning process includes:

forming a first material layer over the substrate;

forming a resist layer over the first material layer;

patterning the resist layer;

etching the first material layer using the patterned resist layer as an etch mask, thereby forming a first pattern in the first material layer, wherein the first pattern corresponds to the first line pattern, the second line pattern, and the dummy pattern; and

thereafter removing the patterned resist layer.

4. The method of claim 3, wherein the first patterning process further includes:

forming spacers on sidewalls of the first pattern;

removing the first pattern; and

etching the substrate with the spacers as an etch mask.

5. The method of claim 1, wherein the first and second line patterns have different line widths.

6. The method of claim 1, wherein a portion of the dummy pattern is oriented lengthwise in a second direction that intersects the first direction with an angle not more than 45 degrees.

7. The method of claim 1, wherein:

the first layout block includes a first plurality of line patterns, one of which is the first line pattern;

the second layout block includes a second plurality of line patterns, one of which is the second line pattern;

the first plurality are oriented lengthwise in the first direction, spaced from each other with a first pitch and along a second direction that is orthogonal to the first direction;

the second plurality are oriented lengthwise in the first direction, spaced from each other with a second pitch and along the second direction; and

the first and second pitches are different.

8. The method of claim 7, wherein each of the first plurality has a first line width, each of the second plurality has a second line width, and the first and second line widths are different.

9. The method of claim 1, wherein the second layout block further includes a third line pattern that is oriented lengthwise in the first direction and is spaced from the second line pattern, further comprising:

adding a second dummy pattern in the first space, wherein the second dummy pattern connects the first and third line patterns.

10. A method, comprising:

receiving an integrated circuit (IC) design layout, wherein the IC design layout includes a first layout block and a second layout block, the first layout block includes a first plurality of line patterns that are oriented lengthwise in a first direction and spaced from each other with a first pitch along a second direction that is orthogonal to the first direction, the second layout block includes a second plurality of line patterns that are oriented lengthwise in the first direction and spaced from each other with a second pitch along the second direction, and the first and second layout blocks are separated by a first space, wherein the first plurality of line patterns are physically separate from the second plurality of line patterns;

adding a dummy pattern to the first space, wherein the dummy pattern physically connects one of the first plurality and one of the second plurality, wherein the dummy pattern is designed to be transferred onto a wafer;

outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format, wherein the mandrel pattern layout includes the first and second pluralities and the dummy pattern, and wherein the cut pattern layout includes a pattern corresponding to the first space;

manufacturing a first mask with the mandrel pattern layout; and

manufacturing a second mask with the cut pattern layout.

11. The method of claim 10, further comprising:

adding another dummy pattern to the first space that connects the one of the first plurality and another one of the second plurality.

12. The method of claim 11, wherein the one of the second plurality is adjacent to the other one of the second plurality.

13. The method of claim 10, wherein each of the first plurality has a first line width, each of the second plurality has a second line width, and the first and second line widths are different.

14. The method of claim 13, wherein the first pitch is different from the second pitch.

15. The method of claim 10, further comprising:

performing a first patterning process to a substrate with the first mask, thereby forming one or more features on the substrate; and

performing a second patterning process to the substrate with the second mask, thereby removing a first portion of the one or more features, wherein the first portion lies in a region corresponding to the first space in the IC design layout.

16. The method of claim 10, wherein a portion of the dummy pattern is oriented lengthwise in a third direction that intersects the first direction with an angle not more than 45 degrees.

17. A method, comprising:

receiving an integrated circuit (IC) design layout, wherein the IC design layout includes two layout blocks separated by a space, wherein each layout block includes a line pattern oriented lengthwise in a first direction, and the two line patterns are physically separate from each other;

adding a dummy pattern to the space, wherein the dummy pattern physically connects the two line patterns of the two layout blocks, wherein a portion of the dummy pattern is oriented lengthwise in a second direction that intersects the first direction with an angle not more than 45 degrees;

outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format, wherein the mandrel pattern layout includes the two line patterns and the dummy pattern, and wherein the cut pattern layout includes a pattern corresponding to the space;

manufacturing a first mask with the mandrel pattern layout; and

manufacturing a second mask with the cut pattern layout.

18. The method of claim 17, wherein the two line patterns have different line widths.