Systems and methods for reducing standby power in floating body memory devices

• US 9,947,387 B2
• Filed: 11/28/2016
• Issued: 04/17/2018
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto
• Primary Examiner(s): Le, Vu
• Application Number:
  US15/361,627
• Publication Number:
  US 20170076784A1
• Time in Patent Office: 505 Days
• Field of Search: 365226, 365229, 365174, 365154, 365155
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Claims

1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells arranged in a column and row configuration for storing charge representative of data, said method comprising:

identifying at least one row or column of cells storing data that is no longer needed; and

setting each of said cells in said at least one row or column to state 0.

2. The method of claim 1, wherein said at least one row or column stores data redundantly.

3. The method of claim 1, wherein said at least one row or column is selected from the group consisting of:

one or more dummy columns, one or more dummy rows, one or more dummy rows and columns, one or more redundant columns, one or more redundant rows, one or more redundant rows and columns, and one or more redundant blocks.

4. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells arranged in a column and row configuration,

wherein each of said plurality of floating body memory cells comprises at least two stable floating body charge levels,

wherein a standby power of one of said at least two stable floating body charge levels is lower than a standby power of the other of said at least two stable floating body charge levels,

wherein said method comprises:

identifying at least one row or column of cells storing data that is no longer needed; and

setting each of said cells in said at least one row or column to said floating body charge level having the lower standby power.

5. The method of claim 4, wherein said at least one row or column stores data redundantly.

6. The method of claim 4, wherein said at least one row or column is selected from the group consisting of:

one or more dummy columns, one or more dummy rows, one or more dummy rows and columns, one or more redundant columns, one or more redundant rows, one or more redundant rows and columns, and one or more redundant blocks.

7. A floating body memory cell having at least two stable floating body charge levels, wherein the standby power of one of said at least two stable floating body charge levels is lower than the other of said at least two stable floating body charge levels;

and

means for reducing standby power of said floating body memory cell, wherein said means for reducing standby power comprises means for temporarily disabling a vertical bipolar holding mechanism of said floating body memory cell.

8. The floating body memory cell of claim 7, further comprising a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type.

9. The floating body memory cell of claim 8, further comprising a back-bias region having a second conductivity type selected from a p-type conductivity type and an n-type conductivity type, wherein said second conductivity type is different from said first conductivity type.

10. The floating body memory cell of claim 9, wherein applying a back-bias to said back-bias region results in maintenance of said floating body charge levels.

11. The floating body memory cell of claim 10, wherein said voltage applied to said back-bias region is a constant positive voltage bias.

12. The floating body memory cell of claim 10, wherein said voltage applied to said back-bias region is a periodic pulse of positive voltage.

13. The floating body memory cell of claim 7, wherein said means for reducing standby power of said floating body memory cell comprises means for identifying whether at least one of said stable charge levels remains currently needed for storage of data by said floating body memory cell.

14. The floating body memory cell of claim 7, wherein said means for reducing standby power comprises means for identifying when said floating body memory cell stores data that is not being actively used.

15. The floating body memory cell of claim 7, wherein said means for reducing standby power comprises means for identifying when said floating body memory cell does not store any valid data.