Wire bond support structure and microelectronic package including wire bonds therefrom

• US 9,947,641 B2
• Filed: 07/22/2016
• Issued: 04/17/2018
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Co, Reynaldo, Zohni, Wael, Cizek, Rizza Lee Saga, Katkar, Rajesh
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US15/217,084
• Publication Number:
  US 20160329308A1
• Time in Patent Office: 634 Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11318 by dispensing droplets
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

Claims

1. A method of making a structure, comprising:

joining wire bonds of a support structure to a substrate having a first region and a second region, wherein the substrate has a first surface and a second surface remote from the first surface and a plurality of conductive elements at the first surface, wherein the support structure has a third surface and a fourth surface remote from the third surface and second electrically conductive elements exposed at the third surface, the second electrically conductive elements being electrically connected to the conductive elements at a first portion of the first surface of the substrate by wire bonds, wherein the wire bonds define edge surfaces, have ends and have bases remote from the ends and electrically connected to the second electrically conductive elements, wherein the joining includes bonding the ends with respective ones of the conductive elements at the second region of the first surface of the substrate by flowing third electrically conductive elements through which the respective ones of the conductive elements at the first surface are electrically connected with the ends of the wire bonds; and

forming a dielectric element on the substrate and removing the support structure, wherein the dielectric element is formed overlying and extending from the second region of the first surface and filling spaces between and covering portions of the wire bonds such that the covered portions of the wire bonds are separated from one another by the dielectric element, wherein unencapsulated portions of the second electrically conductive elements are defined by portions of the second electrically conductive elements that are uncovered by the encapsulation layer when the support structure is removed, the unencapsulated portions including surfaces of the second electrically conductive elements remote from the bases of the wire bonds, the dielectric element overlying at least the first region of the first surface, the first region being other than the second region and having an area sized to accommodate an entire area of at least one microelectronic element.

2. The method of claim 1, wherein the third electrically conductive elements include at least one of solder or a conductive paste.

3. The method of claim 1, wherein the encapsulation layer includes a surface remote from the substrate uncovering the unencapsulated portions of the second electrically conductive elements.

4. The method of claim 1, further comprising:

forming a redistribution layer extending along at least a portion of a surface of the encapsulation layer remote from the first surface of the substrate and defining the uncovered portions of the second electrically conductive elements,

wherein the redistribution layer includes a redistribution substrate having a fifth surface adjacent the surface of the encapsulation layer and a sixth surface remote from the fifth surface, first electrically conductive pads at the fifth surface of the redistribution substrate aligned with respective ones of the bases of the wire bonds facing the uncovered portions of the third electrically conductive elements, and second electrically conductive pads at the fourth surface of the redistribution substrate electrically connected with the first conductive pads.

5. The method of claim 1 further comprising:

forming a thermally conductive layer element overlying and in thermal communication with a surface of the microelectronic element remote from the first surface of the substrate and disposed within a recess of the encapsulation layer.

6. The method of claim 1 further comprising:

forming thermally conductive elements overlying and in thermal communication with a surface of the microelectronic element remote from the first surface of the substrate and portions of the first surface at the second region, wherein the encapsulation layer is formed after the forming of the thermally conductive elements.

7. A method for forming a microelectronic package, comprising:

forming wire bonds on contacts on a temporary support structure, the wire bonds having bases attached to the contacts and having ends remote from the bases;

forming a microelectronic assembly separately from the temporary support structure, the microelectronic assembly having conductive elements;

joining the ends of the wire bonds to the conductive elements of the microelectronic assembly with conductive masses, wherein the joining defines a region between facing surfaces of the temporary support structure and the microelectronic assembly;

forming a dielectric layer in the region on portions of the conductive masses and the wire bonds therein; and

removing the temporary support structure.

8. The method according to claim 7, wherein the forming of the wire bonds on the contacts on the temporary support structure comprises:

attaching a release layer to a surface of a temporary substrate; and

forming a metalization layer on a surface of the release layer to provide the contacts.

9. The method according to claim 8, wherein the forming of the metalization layer comprises patterning a metal foil to provide pads as the contacts.

10. The method according to claim 7, wherein the forming a microelectronic assembly comprises mounting a semiconductor chip to a surface of a substrate.

11. The method according to claim 10, further comprising providing spacers extending from the surface of the substrate of the microelectronic assembly.

12. The method according to claim 11, wherein the dielectric layer is a first dielectric layer, the method further comprising forming a second dielectric layer between a surface of the semiconductor chip and the surface of the substrate of the microelectronic assembly.

13. The method according to claim 10, further comprising providing thermal elements extending from the surface of the substrate of the microelectronic assembly.

14. The method according to claim 10, wherein the conductive elements are interconnected to the semiconductor chip by traces of the substrate.

15. The method according to claim 10, wherein the conductive elements are pads having contact surfaces.

16. The method according to claim 15, wherein the conductive masses are disposed on the contact surfaces.

17. The method according to claim 16, further comprising reflowing the conductive masses prior to the joining.

18. The method according to claim 7, wherein the contacts are of a redistribution layer.

19. The method according to claim 7, further comprising forming a heat spreader with formation of the contacts.

20. A method for forming a microelectronic package, comprising:

forming wire bonds on a temporary support structure, the wire bonds having bases and ends remote from the bases;

forming a microelectronic assembly separately from the temporary support structure, the microelectronic assembly having conductive elements;

joining the ends of the wire bonds to the conductive elements of the microelectronic assembly with conductive masses, wherein the joining defines a region between facing surfaces of the temporary support structure and the microelectronic assembly;

forming a dielectric layer in the region on portions of the conductive masses and the wire bonds therein;

removing the temporary support structure; and

forming a redistribution layer interconnected to the bases.