Semiconductor device and a method for fabricating the same

• US 9,947,657 B2
• Filed: 04/04/2016
• Issued: 04/17/2018
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Fang, Liaw, Jhon Jhy, Liang, Min-Chang
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US15/090,202
• Publication Number:
  US 20170221891A1
• Time in Patent Office: 743 Days
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Claims

1. A semiconductor device including a fin field effect transistor, comprising:

a first gate electrode disposed between gate sidewall spacers made of an insulating material;

a first source/drain (S/D) region disposed adjacent to the first gate electrode;

a first S/D contact made of a conductive material and disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode;

a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact;

a first contact layer made of a conductive material and being in direct contact with the first gate electrode and an uppermost portion and a side face of the first S/D contact; and

a first wiring layer integrally formed with the first contact layer, wherein;

there is no interface between the first contact layer and the first wiring layer in a cross sectional view, and

the first contact layer has a smaller area than the first wiring layer in plan view.

2. The semiconductor device of claim 1, further comprising a first gate cap insulating layer formed over the first gate electrode,

wherein a side surface of the first contact layer is in contact with the first gate cap insulating layer.

3. The semiconductor device of claim 1,

wherein a bottom surface of the first contact layer is in contact with an upper surface of the first spacer layer and an upper surface of the one of the gate sidewall spacers.

4. The semiconductor device of claim 2, further comprising a first interlayer dielectric layer disposed over at least the first cap insulating layer, wherein:

the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer, and

the first contact layer penetrates a bottom portion of the first interlayer dielectric layer and the first gate cap insulating layer.

5. The semiconductor device of claim 4, further comprising:

a second gate electrode;

a gate contact plug made of a conductive material and being disposed on the second gate electrode;

a second contact layer made of a conductive material and being in contact with the gate contact plug; and

a second wiring layer integrally formed with the second contact layer, wherein;

there is no interface between the second contact layer and the second wiring layer in a cross sectional view,

the second wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the second contact layer penetrates the bottom portion of the first interlayer dielectric layer and a second gate cap insulating layer.

6. The semiconductor device of claim 5, further comprising:

a second S/D region;

a second S/D contact disposed on the second S/D region;

a third contact layer made of a material and being in contact with the second S/D contact; and

a third wiring layer integrally formed with the third contact layer, wherein;

there is no interface between the third contact layer and the third wiring layer in a cross sectional view,

the third wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the third contact layer penetrates the bottom portion of the first interlayer dielectric layer.

7. The semiconductor device of claim 6, further comprising a fin structure, wherein:

the first contact layer and the third contact layer are disposed over the fin structure in plan view, and

the second contact layer is not disposed over the fin structure in plan view.

8. The semiconductor device of claim 6, wherein upper surfaces of the first S/D contact, the second S/D contact and the gate contact plug are located substantially at a same plane.

9. The semiconductor device of claim 1, wherein:

the first S/D contact includes at least one conductive material selected the group consisting of Co, Ni, W and Mo, and

the first contact layer includes at least one conductive material selected the group consisting of TiN, Ti, Cu and Al.

10. A semiconductor device including a fin field effect transistor, comprising:

a first gate electrode disposed between gate sidewall spacers made of an insulating material;

a first gate contact layer made of a first conductive material and being disposed on the first gate electrode;

a first source/drain (S/D) region disposed adjacent to the first gate electrode;

a first S/D contact made of a conductive material and being disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode;

a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact;

a first contact layer made of a conductive material and being in direct contact with an uppermost portion of the first gate contact layer and an uppermost portion of the first S/D contact;

a first interlayer dielectric layer disposed over the first gate contact layer and the first S/D contact; and

a first wiring layer integrally formed with the first contact layer, wherein;

there is no interface between the first contact layer and the first wiring layer in a cross sectional view,

the first contact layer has a smaller area than the first wiring layer in plan view,

the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer,

the first contact layer penetrates a bottom portion of the first interlayer dielectric layer,

the first wiring layer protrudes.

11. The semiconductor device of claim 10,

wherein a bottom surface of the first contact layer is in contact with an upper surface of the first spacer layer and an upper surface of the one of the gate sidewall spacers.

12. The semiconductor device of claim 10, further comprising:

a second gate electrode;

a second gate contact layer disposed on the second gate electrode;

a second contact layer made of a conductive material and being in contact with the second gate contact layer; and

a second wiring layer integrally formed with the second contact layer, wherein;

there is no interface between the second contact layer and the second wiring layer in a cross sectional view,

the second wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the second contact layer penetrates the bottom portion of the first interlayer dielectric layer.

13. The semiconductor device of claim 12, further comprising:

a second S/D region;

a second S/D contact made of a conductive material and being disposed on the second S/D region;

a third contact layer made of a conductive material and being in contact with the second S/D contact; and

a third wiring layer integrally formed with the third contact layer, wherein;

there is no interface between the third contact layer and the third wiring layer in a cross sectional view,

the third wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the third contact layer penetrates the bottom portion of the first interlayer dielectric layer.

14. The semiconductor device of claim 13, further comprising a fin structure, wherein:

the third contact layer is disposed over the fin structure in plan view, and

the first and second contact layers are not disposed over the fin structure in plan view.

15. The semiconductor device of claim 13, wherein upper surfaces of the first S/D contact, the second S/D contact and the gate contact layer are located substantially at a same plane.

16. The semiconductor device of claim 13, wherein bottom surfaces of the first contact layer, the second contact layer and the third contact layer are located substantially at a same plane.

17. The semiconductor device of claim 10, wherein the first gate contact layer includes at least one conductive material selected the group consisting of Co, W and Mo.

18. A method of manufacturing a semiconductor device including a fin field effect transistor, the method comprising:

forming a gate structure over a fin structure, the gate structure including a gate electrode layer disposed between gate sidewall spacers made of an insulating material and a cap insulating layer;

forming a source/drain (S/D) contact, the S/D contact being not in direct contact with the gate electrode and passing through an insulating layer formed adjacent to the gate spacer layers and contacting an S/D structure;

forming an interlayer dielectric layer;

etching a part of the interlayer dielectric layer, a part of the cap insulating layer, a part of one of the gate sidewall spacers and a part of the insulating layer, thereby forming an opening in which at least a part of an upper surface of the gate electrode layer and at least a part of an upper surface and at least a part of a side surface of the S/D contact are exposed; and

forming a contact layer and a first wiring layer by filling the opening with a conductive material, wherein;

the contact layer is electrically connected to the gate electrode layer and the S/D contact and overlaps the gate electrode and the S/D contact layer in plan view.

19. The method of claim 18, wherein the contact layer is in direct contact with the gate electrode and the S/D contact.

20. The method of claim 18, wherein:

the S/D contact includes at least one conductive material selected the group consisting of Co, Ni, W and Mo, and

the contact layer is includes at least one conductive material selected the group consisting of Ti, TiN, Cu and Al.

21. The method of claim 20, wherein the gate contact layer includes at least one conductive material selected the group consisting of Co, W and Mo.