Semiconductor device and a method for fabricating the same
First Claim
1. A semiconductor device including a fin field effect transistor, comprising:
- a first gate electrode disposed between gate sidewall spacers made of an insulating material;
a first source/drain (S/D) region disposed adjacent to the first gate electrode;
a first S/D contact made of a conductive material and disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode;
a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact;
a first contact layer made of a conductive material and being in direct contact with the first gate electrode and an uppermost portion and a side face of the first S/D contact; and
a first wiring layer integrally formed with the first contact layer, wherein;
there is no interface between the first contact layer and the first wiring layer in a cross sectional view, andthe first contact layer has a smaller area than the first wiring layer in plan view.
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Accused Products
Abstract
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.
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Citations
21 Claims
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1. A semiconductor device including a fin field effect transistor, comprising:
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a first gate electrode disposed between gate sidewall spacers made of an insulating material; a first source/drain (S/D) region disposed adjacent to the first gate electrode; a first S/D contact made of a conductive material and disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode; a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact; a first contact layer made of a conductive material and being in direct contact with the first gate electrode and an uppermost portion and a side face of the first S/D contact; and a first wiring layer integrally formed with the first contact layer, wherein; there is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device including a fin field effect transistor, comprising:
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a first gate electrode disposed between gate sidewall spacers made of an insulating material; a first gate contact layer made of a first conductive material and being disposed on the first gate electrode; a first source/drain (S/D) region disposed adjacent to the first gate electrode; a first S/D contact made of a conductive material and being disposed on the first S/D region, the S/D contact being not in direct contact with the first gate electrode; a first spacer layer made of an insulating material and disposed between one of the gate sidewall spacers and the first S/D contact; a first contact layer made of a conductive material and being in direct contact with an uppermost portion of the first gate contact layer and an uppermost portion of the first S/D contact; a first interlayer dielectric layer disposed over the first gate contact layer and the first S/D contact; and a first wiring layer integrally formed with the first contact layer, wherein; there is no interface between the first contact layer and the first wiring layer in a cross sectional view, the first contact layer has a smaller area than the first wiring layer in plan view, the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer, the first contact layer penetrates a bottom portion of the first interlayer dielectric layer, the first wiring layer protrudes. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method of manufacturing a semiconductor device including a fin field effect transistor, the method comprising:
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forming a gate structure over a fin structure, the gate structure including a gate electrode layer disposed between gate sidewall spacers made of an insulating material and a cap insulating layer; forming a source/drain (S/D) contact, the S/D contact being not in direct contact with the gate electrode and passing through an insulating layer formed adjacent to the gate spacer layers and contacting an S/D structure; forming an interlayer dielectric layer; etching a part of the interlayer dielectric layer, a part of the cap insulating layer, a part of one of the gate sidewall spacers and a part of the insulating layer, thereby forming an opening in which at least a part of an upper surface of the gate electrode layer and at least a part of an upper surface and at least a part of a side surface of the S/D contact are exposed; and forming a contact layer and a first wiring layer by filling the opening with a conductive material, wherein; the contact layer is electrically connected to the gate electrode layer and the S/D contact and overlaps the gate electrode and the S/D contact layer in plan view. - View Dependent Claims (19, 20, 21)
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Specification