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Driver circuit comprising semiconductor device

  • US 9,947,695 B2
  • Filed: 10/24/2016
  • Issued: 04/17/2018
  • Est. Priority Date: 10/16/2009
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • first to eighth transistors,first and second capacitors;

    wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,wherein one of source and drain of the fourth transistor is electrically connected to a gate of the second transistor,wherein a first electrode of the first capacitor is electrically connected to the gate of the second transistor,wherein a second electrode of the first capacitor is electrically connected to the other of source and drain of the second transistor,wherein one of source and drain of the fifth transistor is electrically connected to one of source and drain of the sixth transistor,wherein one of source and drain of the seventh transistor is electrically connected to a gate of the fifth transistor,wherein one of source and drain of the eighth transistor is electrically connected to a gate of the sixth transistor,wherein a first electrode of the second capacitor is electrically connected to the gate of the sixth transistor,wherein a second electrode of the second capacitor is electrically connected to the other of source and drain of the sixth transistor,wherein power supply voltage is supplied to the other of source and drain of the second transistor,wherein the power supply voltage is supplied to the other of source and drain of the sixth transistor,wherein the one of source and drain of the first transistor is electrically connected to a first output terminal,wherein the other of source and drain of the third transistor is electrically connected to a first input terminal,wherein the one of source and drain of the fifth transistor is electrically connected to a second output terminal, andwherein the other of source and drain of the seventh transistor is electrically connected to a second input terminal.

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