Display device, array substrate, and thin film transistor

• US 9,947,757 B2
• Filed: 03/21/2016
• Issued: 04/17/2018
• Est. Priority Date: 04/28/2012
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Yuan, Guangcai, Lee, Woobong
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US15/075,579
• Publication Number:
  US 20160204216A1
• Time in Patent Office: 757 Days
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method for manufacturing the thin film transistor, including: forming a gate, an active layer and a gate insulating layer disposed between the gate and the active layer; wherein the gate insulating layer is in a double-layer structure comprising a first gate insulating layer next to the gate and a second gate insulating layer next to the active layer, and one of the first gate insulating layer and the second gate insulating layer is annealed.

Claims

1. A method for manufacturing the thin film transistor, comprising:

sequentially forming an active layer, a gate insulating layer and a gate on a base substrate;

wherein the active layer is an oxide semiconductor, and the gate insulating layer is in a double-layer structure comprising a first gate insulating layer next to the gate and a second gate insulating layer next to the active layer, and

wherein forming of the gate insulating layer comprises;

forming the second gate insulating layer without annealing on the active layer;

forming the first gate insulating layer on the second gate insulating layer; and

performing an annealing process on the first gate insulating layer; and

the annealing process comprises;

the first gate insulating layer being dehydrogenized with a high temperature annealing furnace,

the annealing process being carried out under the protection of nitrogen gas, vacuum, or rare gas, in which annealing temperature is 250°

C.˜

450°

C. and annealing time is 20 min˜

150 min.

2. The method for manufacturing the thin film transistor according to claim 1, wherein at least one of the first gate insulating layer and the second gate insulating layer is an inorganic insulating thin film.

3. The method for manufacturing the thin film transistor according to claim 2, wherein the first gate insulating layer is formed of silicon nitride or silicon oxynitride.

4. The method for manufacturing the thin film transistor according to claim 3, wherein the second gate insulating layer is formed of silicon oxide, yttrium oxide, or silicon oxynitride.

5. The method for manufacturing the thin film transistor according to claim 1, wherein the first gate insulating layer has a thickness of 50 nm˜

600 nm.

6. The method for manufacturing the thin film transistor according to claim 5, wherein the first gate insulating layer has a thickness of 100 nm˜

300 nm.

7. The method for manufacturing the thin film transistor according to claim 1, wherein the second gate insulating layer has a thickness of 50 nm˜

650 nm.

8. The method for manufacturing the thin film transistor according to claim 7, wherein the second gate insulating layer has a thickness of 100 nm˜

200 nm.

9. A method for manufacturing the thin film transistor, comprising:

sequentially forming an active layer, a gate insulating layer and a gate on a base substrate;

wherein the active layer is an oxide semiconductor, and the gate insulating layer is in a double-layer structure comprising a first gate insulating layer next to the gate and a second gate insulating layer next to the active layer, and

wherein forming of the gate insulating layer comprises;

forming the second gate insulating layer without annealing on the active layer;

forming the first gate insulating layer on the second gate insulating layer; and

performing an annealing process on the first gate insulating layer, and

wherein the annealing process comprises;

within a vacuum heating chamber being incorporated into a plasma enhanced chemical vapor deposition (PECVD) apparatus for sequentially forming the active layer, the gate insulating layer and the gate, in which the pressure is 10<sup>−

4</sup> Pa˜

1 Pa,

a dehydrogenizing process being performed on the first gate insulating layer, in which the temperature of the vacuum heating chamber is 350°

C.˜

480°

C., and an annealing time period is 10 min˜

30 min.