Power MOSFET having lateral channel, vertical current path, and P-region under gate for increasing breakdown voltage

• US 9,947,779 B2
• Filed: 07/28/2017
• Issued: 04/17/2018
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Pu, Kui, Su, Shih-Tzung
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/663,465
• Publication Number:
  US 20170330962A1
• Time in Patent Office: 263 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7812 with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Claims

1. A transistor comprising:

a first semiconductor layer;

a buried layer of a first conductivity type over the first semiconductor layer;

a sinker region of the first conductivity type extending from a top semiconductor surface to the buried layer;

a first region of the first conductivity type overlying the buried layer;

a trench formed in the first region, the trench having a first sidewall and an opposing second sidewall;

a conductive field plate formed in the trench;

a well region of a second conductivity type formed in a top surface of the first region facing the first sidewall of the trench;

a source region of the first conductivity type formed in the well region, wherein an area between an edge of the well region and the source region forms a lateral channel of a MOSFET;

a conductive lateral gate insulated from and overlying the channel, the gate extending over the trench and extending beyond the first sidewall and second sidewall of the trench;

a second region of the second conductivity type facing the second sidewall of the trench, wherein the gate is insulated from and overlying the second region, and wherein no channel is formed in the second region;

a drain electrode formed over and contacting the sinker region; and

a source electrode coupled to the well region and the source region,

wherein the transistor is configured such that biasing the gate to turn on the transistor inverts the lateral channel to conduct a lateral current from the source electrode through the channel, which flows to the buried layer and is laterally conducted to the sinker region, which then flows to the drain electrode, and

wherein biasing the gate also inverts the surface of the second region.

2. The transistor of claim 1 wherein the conductive field plate is connected to the gate.

3. The transistor of claim 1 wherein the conductive field plate is connected to the source electrode.

4. The transistor of claim 1 wherein the conductive field plate is floating.

5. The transistor of claim 1 wherein the conductive field plate is deeper than the well region.

6. The transistor of claim 1 wherein the conductive field plate and a dopant concentration of the first region are configured to enhance lateral depletion of the first region in the transistor'"'"'s off-state so that the first region is fully depleted at a breakdown voltage of the transistor.

7. The transistor of claim 1 wherein the gate has a vertical extension running alongside the conductive field plate in the trench.

8. The transistor of claim 7 wherein the vertical extension of the gate inverts a portion of the well region abutting the first sidewall of the trench.

9. The transistor of claim 7 further comprising an enhanced doping region of the first conductivity type between the well region and the first sidewall of the trench, wherein the vertical extension of the gate is insulated from and opposes the enhanced doping region for reducing on-resistance.

10. The transistor of claim 1 wherein the well region extends to the first sidewall of the trench.

11. The transistor of claim 1 further comprising a substrate contact on a bottom surface of the transistor, the substrate contact being electrically connected to the source electrode.

12. The transistor of claim 1 wherein the first semiconductor layer is a substrate.

13. The transistor of claim 12 wherein the substrate is of the second conductivity type.

14. The transistor of claim 1 further comprising an insulating layer overlying the first semiconductor layer, wherein the buried layer is formed over the insulating layer.

15. The transistor of claim 1 further comprising a second conductive field plate surrounding the sinker region.

16. The transistor of claim 1 wherein the first conductivity type is an N-type and the second conductivity type is a P-type.