Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same

• US 9,947,786 B2
• Filed: 11/16/2015
• Issued: 04/17/2018
• Est. Priority Date: 04/03/2015
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Young Bae, Kim, Kwang Il
• Primary Examiner(s): Malek, Maliheh
• Application Number:
  US14/942,527
• Publication Number:
  US 20160293758A1
• Time in Patent Office: 883 Days
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.

Claims

1. A semiconductor device comprising:

a high voltage transistor and a junction field effect transistor (JFET) formed on a substrate, wherein

the JFET comprises

a first conductivity type deep-well region comprising a diffusion region located on the substrate,

a second conductivity type buried impurity layer located on the first conductivity type deep-well region,

a first conductivity type common drain region located on the first conductivity type deep-well region,

a first conductivity type first source region located on the first conductivity type deep-well region,

a second conductivity type pick-up region formed on the substrate, and

an insulating layer formed on the substrate between the first conductivity type common drain region and the first conductivity type first source region, wherein

the diffusion region has an impurity concentration that is lower than other portions of the first conductivity type deep-well region.

2. The semiconductor device of claim 1, wherein the high voltage transistor comprises:

a gate electrode located on the substrate; and

a second source region located around the gate electrode, wherein

the first conductivity type common drain region is located a certain distance apart from the gate electrode.

3. The semiconductor device of claim 1, wherein a groove is located on a lower side of the diffusion region.

4. The semiconductor device of claim 3, wherein a pinch-off region is located in the diffusion region.

5. The semiconductor device of claim 1, further comprising:

a first terminal connected to the first conductivity type common drain region;

a second terminal connected to the first conductivity type first source region; and

a third terminal connected to the pick-up region, wherein

the first and second terminals are electrically connected to the first conductivity type deep-well region,

the third terminal is electrically connected to the substrate, and

in response to a first voltage, which is a voltage difference between the first terminal and the third terminal, being or larger than a pinch-off voltage, a depletion region is formed in the first conductivity type deep-well region.

6. The semiconductor device of claim 5, wherein in response to the first voltage being smaller than the pinch-off voltage, the output voltage of the second terminal is proportionate to the first voltage, and wherein in response to the first voltage being the same or larger than the pinch-off voltage, a voltage of the second terminal becomes a fixed voltage.

7. The semiconductor device of claim 1, wherein the second conductivity type buried impurity layer is formed to be in contact with a lower side of the insulating layer or formed separately in a vertical direction of a substrate surface.

8. The semiconductor device of claim 1, wherein the first conductivity type deep-well region comprises a first deep-well region and a second deep-well region, and

the diffusion region is located between the first deep-well region and the second deep-well region and formed by an impurity diffusion of the first deep-well region and the second deep-well region.

9. The semiconductor device of claim 8, wherein the first deep-well region has a higher doping concentration of an impurity than the second deep-well region and/or is formed to be deeper than the second deep-well region.

10. The semiconductor device of claim 1, wherein the diffusion region comprises a first deep-well region and a second deep-well region formed by ion injection of a first conductivity type impurity on the substrate using a mask pattern with a predetermined width, wherein the diffusion region is formed through a thermal processing process that diffuses the first conductive type impurity.

11. A semiconductor device comprising:

a first conductivity type deep-well region located on a substrate;

a second conductivity type buried impurity layer located on the first conductivity type deep-well region;

a first conductivity type first drain region and a first source region located on the first conductivity type deep-well region;

a second conductivity type first pick-up region located on the substrate;

an insulating layer located on a surface of the substrate between the first conductivity type first drain region and the first source region; and

a junction field effect transistor (JFET) gate region formed on a part of the first conductivity type deep-well region, formed to be in contact with a lower part of the insulating layer, and formed to pass through the second conductivity type buried impurity layer.

12. The semiconductor device of claim 11, comprising:

a high voltage transistor located on the first conductivity type deep-well region, wherein

the high voltage transistor comprises

a gate electrode,

a second source region and a second pick-up region located on a side of the gate electrode, and

a second drain region located separated by a certain distance from the gate electrode,

wherein the first drain region and the second drain region are identical.

13. The semiconductor device of claim 12, wherein the JFET gate region and the second pick-up region are electrically connected.

14. The semiconductor device of claim 11, further comprising:

a first terminal connected to the first drain region;

a second terminal connected to the first source region; and

a third terminal connected to the pick-up region;

wherein

the first and second terminals are electrically connected to the first conductivity type deep-well region,

the third terminal is electrically connected to the substrate, and

in response to a first voltage, which is a voltage difference between the first terminal and the third terminal, being the same or larger than the pinch-off voltage, a depletion region is formed in the first conductivity type deep-well region, and

in response to the first voltage being smaller than the pinch-off voltage, the output voltage of the second terminal is proportional to the first voltage and in response to the first voltage being equal to or larger than a pinch-off voltage, a voltage of the second terminal becomes a fixed voltage.

17. The semiconductor device of claim 14, further comprising a JFET gate region formed to pass through the second conductivity type impurity layer.

15. A semiconductor device comprising:

a first conductivity type deep-well region having a first concentration and located on a substrate;

a first conductivity type semiconductor region having a second concentration that is lower in concentration than the first concentration and located in the first conductivity type deep-well region;

a second conductivity type impurity layer that is located on the first conductivity type deep-well region;

a first conductivity type drain region and a source region that are located separately from the semiconductor region; and

a second conductivity type pick-up region located on the substrate, wherein

the second conductivity type impurity layer is in contact with the semiconductor region, and

a pinch-off voltage is generated through the semiconductor region.

16. The semiconductor device of claim 15, wherein the first conductivity type deep-well region comprises a first deep-well region and a second deep-well region,

the first deep-well region and the second deep-well region are located to be in contact with the semiconductor region, and

wherein the first conductivity type deep-well region is formed by diffusion of a first conductivity type dopant in the first deep-well region and the second deep-well region.

18. A junction field effect transistor (JFET) comprising:

a deep-well region comprising a diffusion region and located on a substrate,

a buried impurity layer,

a common drain region,

a first source region located on the deep-well region, and

a pick-up region and an insulating layer each located on the substrate,

wherein the insulating layer is located on the substrate between the common drain region and the first source region, and wherein the diffusion region has an impurity concentration that is lower than concentrations of other portions of the deep-well region.

19. The semiconductor device of claim 18, wherein the deep-well region, the common drain region, and the first source region are of a first conductivity type and the buried impurity layer and the pickup-region are of a second conductivity type.

20. The semiconductor device of claim 18, wherein a groove is located on a lower side of the diffusion region.