Vertical pillar-type field effect transistor and method

• US 9,947,793 B1
• Filed: 02/08/2017
• Issued: 04/17/2018
• Est. Priority Date: 02/08/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cheng, Kangguo, Yamashita, Tenko
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US15/427,594
• Time in Patent Office: 433 Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Disclosed is a method of forming a vertical pillar-type field effect transistor (FET). One or more semiconductor pillars are formed by epitaxial deposition in one or more openings, respectively, that extend through a first dielectric layer and that have high aspect ratios in two directions. The first dielectric layer is etched back and the following components are formed laterally surrounding the semiconductor pillar(s): a first source/drain region above and adjacent to the first dielectric layer, a second dielectric layer on the first source/drain region, a gate on the second dielectric layer and a gate cap on the gate. The gate cap extends over the top surface(s) of the semiconductor pillar(s). A recess is formed in the gate cap to expose at least the top surface(s) of the semiconductor pillar(s) and a second source/drain region is formed within the recess. Also disclosed is the vertical pillar-type FET structure.

Claims

1. A method comprising:

forming at least one semiconductor pillar that extends vertically through a first dielectric layer to a substrate;

etching back the first dielectric layer;

forming, above the first dielectric layer and laterally surrounding the semiconductor pillar, a first source/drain region immediately adjacent to the first dielectric layer, a second dielectric layer on the first source/drain region, a gate on the second dielectric layer and a gate cap on the gate, the gate cap further extending over a top surface of the semiconductor pillar;

forming a recess in the gate cap to expose at least the top surface of the semiconductor pillar, a bottom of the recess being above and physically separated from a top of the gate; and

forming a second source/drain region within the recess.

2. The method of claim 1, the semiconductor pillar having a first aspect ratio defined as a ratio of a height of the semiconductor pillar to a first width of the semiconductor pillar in a first direction and further having a second aspect ratio defined as a ratio of the height of the semiconductor pillar to a second width of the semiconductor pillar in a second direction that is perpendicular to the first direction, the first aspect ratio and the second aspect ratio being each greater than 5.

3. The method of claim 2,

the semiconductor pillar being formed by epitaxial deposition,

the first aspect ratio and the second aspect ratio causing substantial defects occurring during the epitaxial deposition of the semiconductor pillar to be trapped within a lower portion of the semiconductor pillar, and

the first source/drain region being formed above and immediately adjacent to the first dielectric layer with the lower portion of the semiconductor pillar that contains the defects being below the first source/drain region and laterally surrounded by the first dielectric layer.

4. The method of claim 2, the first aspect ratio and the second aspect ratio being approximately equal and the semiconductor pillar being any of square and circular in shape.

5. The method of claim 2, the first aspect ratio and the second aspect ratio being different and the semiconductor pillar being any of rectangular, ovular and triangular in shape.

6. The method of claim 1, the substrate comprising a first semiconductor material and the semiconductor pillar comprising a second semiconductor material that is different from the first semiconductor material.

7. The method of claim 6, the first source/drain region and the second source/drain region comprising a third semiconductor material that is different from the second semiconductor material.

8. The method of claim 1,

the first source/drain region having an outer edge portion that extends laterally beyond the gate,

the second source/drain region only partially filling the recess, and

the method further comprising:

forming a first contact opening extending vertically to the outer edge portion of the first source/drain region;

forming a second contact opening extending vertically to the gate; and

depositing a metal layer to fill the first contact opening to form a first source/drain contact, to fill the recess to form a second source/drain contact and to fill the second contact opening to form a gate contact.

9. A method comprising:

forming multiple openings that extend vertically through a first dielectric layer to a semiconductor substrate;

forming semiconductor pillars in the openings such that the semiconductor pillars have bottom surfaces immediately adjacent to the semiconductor substrate and top surfaces opposite the bottom surfaces;

forming dielectric caps within the openings on the top surfaces of the semiconductor pillars;

etching back the first dielectric layer;

forming dielectric spacers on the semiconductor pillars above the first dielectric layer;

forming a first recess in the first dielectric layer below the dielectric spacers and around the semiconductor pillars, the recess leaving lower portions of the semiconductor pillars laterally surrounded by the first dielectric layer and vertical surfaces of the semiconductor pillars exposed between the first dielectric layer and the dielectric spacers;

forming a first source/drain region within the first recess;

forming a second dielectric layer on the first source/drain region;

removing the dielectric caps and any dielectric material of the dielectric spacers above the second dielectric layer;

forming a gate on the second dielectric layer, the gate laterally surrounding the semiconductor pillars and having a gate sidewall spacer;

forming a gate cap on the gate, the gate cap laterally surrounding the semiconductor pillars and further being above and immediately adjacent to the top surfaces of the semiconductor pillars;

forming a second recess in the gate cap to expose at least the top surfaces of the semiconductor pillars, a bottom of the second recess being above and physically separated from a top of the gate; and

forming a second source/drain region within the second recess.

10. The method of claim 9,

each semiconductor pillar having a first aspect ratio defined as a ratio of a height of the semiconductor pillar to a first width of the semiconductor pillar in a first direction and further having a second aspect ratio defined as a ratio of the height of the semiconductor pillar to a second width of the semiconductor pillar in a second direction that is perpendicular to the first direction,

the first aspect ratio and the second aspect ratio being each greater than 5,

the semiconductor pillars being formed by epitaxial deposition,

the first aspect ratio and the second aspect ratio enabling substantial defects occurring during the epitaxial deposition of the semiconductor pillars to be trapped within the lower portions of the semiconductor pillars and

the lower portions of the semiconductor pillars that contain the defects being below the first source/drain region and laterally surrounded by the first dielectric layer.

11. The method of claim 10, the first aspect ratio and the second aspect ratio being approximately equal and each semiconductor pillar being any of square and circular in shape.

12. The method of claim 10, the first aspect ratio and the second aspect ratio being different and each semiconductor pillar being any of rectangular, ovular and triangular in shape.

13. The method of claim 9, the substrate comprising a first semiconductor material, the semiconductor pillars comprising a second semiconductor material that is different from the first semiconductor material, and the first source/drain region and the second source/drain region comprising a third semiconductor material that is different from second semiconductor material.

14. The method of claim 9,

the first source/drain region having an outer edge portion that extends laterally beyond the gate,

the second source/drain region only partially filling the second recess, and

the method further comprising:

forming a first contact opening extending vertically to the outer edge portion of the first source/drain region;

forming a second contact opening extending vertically to the gate; and

depositing a metal layer to fill the first contact opening to form a first source/drain contact, to fill the second recess to form a second source/drain contact and to fill the second contact opening to form a gate contact.