Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

• US 9,947,804 B1
• Filed: 07/24/2017
• Issued: 04/17/2018
• Est. Priority Date: 07/24/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Frougier, Julien, Sung, Min Gyu, Xie, Ruilong, Park, Chanro, Bentley, Steven
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US15/657,659
• Time in Patent Office: 267 Days
• Field of Search: 257288, 257368, 257369, 438151, 438197, 438199, 977762, 977938
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.

Claims

1. A method of forming an integrated circuit (IC) structure, the method comprising:

forming an insulative liner on an upper surface of a substrate, the substrate being included in a precursor structure, the precursor structure having;

a pair of laterally spaced transistor sites defined within the substrate, wherein the insulative liner is formed on the upper surface of the substrate laterally between the pair of transistor sites,

a pair of nanosheet stacks, each positioned on one of the pair of transistor sites, and

a pair of gate structures each positioned on a respective one of the pair of nanosheet stacks;

forming a sacrificial structure on the insulative liner, wherein the sacrificial structure includes;

a semiconductor mandrel positioned on the insulative liner, and

a mask layer positioned on the semiconductor mandrel, wherein an upper surface of the mask layer is positioned above the pair of gate structures;

forming a pair of insulator regions, each of the pair of insulator regions positioned laterally between the sacrificial structure and one of the pair of transistor sites; and

removing the mask layer to expose the upper surface of the semiconductor mandrel; and

epitaxially growing a source/drain epitaxial region between the pair of nanosheet stacks, from exposed sidewalls of the pair of nanosheet stacks and the exposed upper surface of the semiconductor mandrel.

2. The method of claim 1, wherein forming the sacrificial structure further includes:

depositing a sacrificial semiconductor layer over the substrate and the pair of transistor sites;

forming a recess within the sacrificial semiconductor layer laterally between the pair of transistor sites, wherein a lower surface of the recess is substantially aligned with a nanosheet in each of the pair of nanosheet stacks, and wherein the recess includes a pair of sidewalls laterally separated from sidewalls of the pair of transistor sites;

forming the mask layer within the recess; and

removing portions of the sacrificial semiconductor layer not positioned beneath the mask layer, such that a remainder of the sacrificial semiconductor layer defines the semiconductor mandrel after the removing.

3. The method of claim 2, wherein forming the insulative liner on the upper surface of the substrate includes:

forming an insulative coating on exposed surfaces of the substrate, the pair of transistor sites, the pair of nanosheet stacks, and the pair of gate structures; and

removing the insulative coating from exposed surfaces of the pair of transistor sites, the pair of nanosheet stacks, and the pair of gate structures after removing portions of the sacrificial semiconductor layer, such that a remainder of the insulative coating positioned between the substrate and the semiconductor mandrel defines the insulative liner.

4. The method of claim 1, further comprising, before forming the pair of insulator regions:

laterally recessing a set of alternating nanosheets in each of the pair of nanosheet stacks to yield a plurality of lateral recesses in the pair of nanosheet stacks; and

forming an insulative coating on exposed surfaces of the substrate, the pair of transistor sites, the pair of nanosheet stacks, the pair of gate structures, and the sacrificial structure, wherein a portion of the insulative coating fills the plurality of lateral recesses.

5. The method of claim 4, further comprising, after forming the pair of insulator regions, removing the insulative coating from surfaces of the pair of nanosheet stacks, the pair of gate structures, and the sacrificial structure, such that a remaining portion of the insulative coating positioned within the plurality of lateral recesses of the pair of nanosheet stacks defines an inner spacer.

6. The method of claim 1, further comprising, after growing the source/drain epitaxial region:

forming an insulator on each of the pair of gate structures and the source/drain epitaxial region;

forming an opening within the insulator to expose an upper surface of the source/drain epitaxial region between the pair of nanosheet stacks, wherein remaining portions of the insulator define a pair of insulative caps each positioned on one of the pair of gate structures and directly on a portion of the source/drain epitaxial region; and

forming a trench silicide within the opening, such that the trench silicide is positioned on the source/drain epitaxial region and laterally between the pair of insulative caps, wherein a lateral width of each of the pair of insulative caps between the gate structure and the trench silicide is approximately equal to a lateral width of the pair of insulative regions between each of the pair of transistor sites and the semiconductor mandrel.

7. The method of claim 1, wherein the semiconductor mandrel comprises an amorphous semiconductor, and wherein the source/drain epitaxial region comprises a crystalline semiconductor.

8. A method of forming an integrated circuit (IC) structure, the method comprising:

forming a first pair of transistor sites and a second pair of transistor sites from a substrate, wherein a lateral separation distance between the first pair of transistor sites is less than a separation distance between the second pair of transistor sites, and wherein each of the first pair of transistor sites and the second pair of transistor sites includes a pair of nanosheet stacks each positioned on a respective one of the pair of transistor sites, and a pair of gate structures each positioned on a respective one of the pair of transistor sites;

selectively forming an insulative region between the first pair of transistor sites to cover a first portion of the substrate between the first pair of transistor sites, wherein the second pair of transistor sites and a second portion of the substrate between the second pair of transistor sites remain exposed after the selective forming of an insulative liner;

epitaxially growing a first source/drain epitaxial region between the first pair of semiconductor transistor sites, from exposed portions of the pair of nanosheet stacks on the first pair of transistor sites, such that the first source/drain epitaxial region overlies the insulative region; and

epitaxially growing a second source/drain epitaxial region between the second pair of semiconductor transistor sites, from the second portion of the substrate and exposed portions of the pair of nanosheet stacks on the second pair of transistor sites.

9. The method of claim 8, wherein a lower surface of the first source/drain epitaxial region is positioned above a lower surface of the second source/drain epitaxial region, and wherein the second source/drain epitaxial region contacts and overlies the substrate.

10. The method of claim 8, further comprising, before epitaxially growing the first and second source/drain epitaxial regions:

laterally recessing a set of alternating nanosheets in each of the nanosheet stacks over the first and second pairs of transistor sites to yield a plurality of lateral recesses in each nanosheet stack; and

forming an insulative region on exposed surfaces of at least the substrate, the nanosheet stacks, and the gate structures, wherein a portion of the insulative region fills the plurality of lateral recesses.

11. The method of claim 10, further comprising, after forming the insulative region, removing the inner spacer from surfaces of the substrate, the nanosheet stacks, and the gate structures, such that a remaining portion of the insulative region positioned within the plurality of lateral recesses of the nanosheet stacks defines an inner spacer.

12. The method of claim 8, wherein the epitaxial growing of the first source/drain epitaxial region occurs simultaneously with the epitaxial growing of the second source/drain epitaxial region.

13. The method of claim 8, wherein selectively forming the insulative region between the first pair of transistor sites includes:

forming the insulative liner on exposed surfaces of the substrate, the first pair of transistor sites, the second pair of transistor sites, the nanosheet stacks, and the gate structures;

forming a masking layer on the substrate such that the masking layer covers the first pair of transistor sites, the second pair of transistor sites, the nanosheet stacks, and the gate structures;

removing the insulative liner and the masking layer from at least the second portion of the substrate, the nanosheet stacks, and the gate structures, such that a remaining portion of the insulative liner and the masking layer is positioned on the first portion of the substrate and between the first pair of transistor sites;

removing the masking layer from between the first pair of transistor sites to yield a lateral gap therebetween; and

forming an insulator within the lateral gap between the first pair of transistor sites.

14. The method of claim 13, wherein forming the insulator within the lateral gap between the first pair of transistor sites includes:

forming a insulative coating within the lateral gap and on exposed surfaces of the substrate, the second pair of transistor sites, the nanosheet stacks, and the gate structures; and

removing the insulative coating from the second portion of the substrate, the nanosheet stacks, and the gate structures, such that remaining portions of the insulative liner and the insulative coating define the insulator within the lateral gap between the first pair of transistor sites.