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Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

  • US 9,947,804 B1
  • Filed: 07/24/2017
  • Issued: 04/17/2018
  • Est. Priority Date: 07/24/2017
  • Status: Active Grant
First Claim
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1. A method of forming an integrated circuit (IC) structure, the method comprising:

  • forming an insulative liner on an upper surface of a substrate, the substrate being included in a precursor structure, the precursor structure having;

    a pair of laterally spaced transistor sites defined within the substrate, wherein the insulative liner is formed on the upper surface of the substrate laterally between the pair of transistor sites,a pair of nanosheet stacks, each positioned on one of the pair of transistor sites, anda pair of gate structures each positioned on a respective one of the pair of nanosheet stacks;

    forming a sacrificial structure on the insulative liner, wherein the sacrificial structure includes;

    a semiconductor mandrel positioned on the insulative liner, anda mask layer positioned on the semiconductor mandrel, wherein an upper surface of the mask layer is positioned above the pair of gate structures;

    forming a pair of insulator regions, each of the pair of insulator regions positioned laterally between the sacrificial structure and one of the pair of transistor sites; and

    removing the mask layer to expose the upper surface of the semiconductor mandrel; and

    epitaxially growing a source/drain epitaxial region between the pair of nanosheet stacks, from exposed sidewalls of the pair of nanosheet stacks and the exposed upper surface of the semiconductor mandrel.

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