Galvanically isolated DC-DC converter with bidirectional data transmission

• US 9,948,193 B2
• Filed: 06/10/2016
• Issued: 04/17/2018
• Est. Priority Date: 06/10/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Ragonese, Egidio, Spina, Nunzio, Lombardo, Pierpaolo, Greco, Nunzio, Parisi, Alessandro, Palmisano, Giuseppe
• Primary Examiner(s): Finch, III, Fred E
• Application Number:
  US15/178,822
• Publication Number:
  US 20170358993A1
• Time in Patent Office: 676 Days
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H02M 3/33553 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H02M 3/33584 Bidirectional converters
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.

Claims

1. A galvanic isolation system, comprising:

a first galvanically isolated link configured to transfer power from a first circuit to a second circuit across a galvanic barrier; and

a second galvanically isolated link configured to feed back an error signal from the second circuit to the first circuit across the galvanic barrier for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic barrier, said second galvanically isolated link comprising;

a first oscillator of the second circuit providing a radio frequency (RF) control signal modulated by said error signal;

a first transformer having a primary winding coupled to outputs of said first oscillator and a secondary winding coupled to the first circuit;

at least one first electronic switch coupled in series with at least one capacitor coupled to the secondary winding of the first transformer and configured to modify an impedance of the secondary winding to modulate the RF control signal with first data communicated from the first circuit to the second circuit; and

at least one second electronic switch coupled in series with at least one capacitor coupled to the primary winding of the first transformer and configured to modify an impedance of the primary winding to modulate the RF control signal with second data communicated from the second circuit to the first circuit.

2. The system of claim 1, wherein the first galvanically isolated link comprises:

a second oscillator of the first circuit; and

a second transformer having a primary winding coupled to outputs of the first oscillator and a secondary winding coupled to the second circuit.

3. The system of claim 2, wherein the second circuit comprises a rectifier circuit coupled to the secondary winding of the second transformer and configured to convert the power transfer to a DC output voltage.

4. The system of claim 3, wherein the second circuit further comprises an error amplifier configured to determine a difference between the DC output voltage and a reference voltage and generate said error signal in response thereto.

5. The system of claim 4, wherein said error signal changes a peak amplitude of an oscillator signal generated by said first oscillator.

6. The system of claim 5, wherein the first circuit comprises:

a detector circuit coupled to the secondary winding of the first transformer and configured to detect said peak amplitude to generate a control signal; and

a control circuit responsive to said control signal and configured to control the first oscillator to regulate power transfer from the first circuit to the second circuit across the galvanic barrier.

7. The system of claim 6, wherein the control circuit comprises a pulse width modulation (PWM) control circuit responsive to said control signal and configured to generate a PWM switching signal for controlling on and off actuation of the second oscillator.

8. The system of claim 1, wherein the primary of the first transformer comprises two end taps and a center tap, the center tap being coupled to a common node of the second circuit.

9. The system of claim 8, wherein the at least one second electronic switch comprises two electronic switches, each electronic switch coupled to an end tap of the primary of the first transformer and coupled through a series capacitor to said common node of the second circuit.

10. The system of claim 9, wherein each electronic switch is controlled separately by the second encoder.

11. The system of claim 1, wherein the secondary of the first transformer comprises two end taps and a center tap, the center tap being coupled to a common node of the first circuit.

12. The system of claim 11, wherein the at least one first electronic switch comprises two electronic switches, each electronic switch coupled to an end tap of the secondary of the first transformer and coupled through a series capacitor to the common node of the first circuit.

13. The system of claim 12, wherein each electronic switch is controlled separately by the first encoder.