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Device stack with novel gate capacitor topology

  • US 9,948,252 B1
  • Filed: 04/06/2017
  • Issued: 04/17/2018
  • Est. Priority Date: 04/06/2017
  • Status: Active Grant
First Claim
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1. A monolithically integrated circuital arrangement comprising:

  • a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor;

    N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.

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