Device stack with novel gate capacitor topology
First Claim
1. A monolithically integrated circuital arrangement comprising:
- a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor;
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.
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Accused Products
Abstract
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
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Citations
20 Claims
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1. A monolithically integrated circuital arrangement comprising:
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a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor; N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A monolithically integrated circuital arrangement comprising:
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a stack of N transistors arranged in a cascode configuration, comprising an input transistor, M1, and N−
1 cascode transistors, M2, M3, . . . , MN, comprising an output transistor, MN, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor, MN, and a reference voltage provided at a source of the input transistor, M1;N−
1 gate capacitors, C2, C3, . . . , CN−
1, each gate capacitor, Ci, of the N−
1 gate capacitors connected, at a first terminal of the each gate capacitor, Ci, to a gate of a respective transistor, Mi, of the N−
1 cascode transistors, wherein at least one gate capacitor, Ck, of the N−
1 gate capacitors associated to a transistor Mk, is connected, at a second terminal of the at least one gate capacitor, Ck, to a first terminal of a coupling gate capacitor, Ck−
1, of the N−
1 gate capacitors associated to a transistor Mk−
1 adjacent to the transistors Mk, and remaining gate capacitors, C2, C3, . . . , Ck−
2, Ck−
1, Ck+1, . . . , CN, of the N−
1 gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.
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17. A monolithically integrated circuital arrangement comprising:
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a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and a plurality of cascode transistors; a first gate capacitor connected between a gate of a first cascode transistor of the plurality of cascode transistors of the stack and a reference voltage, the first gate capacitor configured to provide a first RF voltage at the gate of the first cascode transistor by way of coupling of an RF voltage at a source of the first cascode transistor; and a second gate capacitor connected between a gate of a second cascode transistor of the plurality of cascode transistor of the stack and the gate of the first cascode transistor, the second gate capacitor configured to couple the first RF voltage to the gate of the second cascode transistor and to further couple an RF voltage at a source of the second cascode transistor to the gate of the second cascode transistor to provide a second RF voltage at the gate of the second cascode transistor, wherein the first RF voltage and the second RF voltage are based on a desired distribution of an RF voltage at an output of the stack across the plurality of transistors of the stack.
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18. A method for realizing a monolithically integrated circuit comprising a stack of a plurality of transistors arranged in a cascode configuration, the method comprising:
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connecting a first gate capacitor between a gate of a first cascode transistor of the stack and a reference voltage; based on the connecting, coupling an RF voltage at a source of the first cascode transistor to the gate of the first cascode transistor, thereby obtaining a first RF voltage at the gate of the first cascode transistor; connecting a second gate capacitor between a gate of a second cascode transistor of the stack and the gate of the first cascode transistor; based on the connecting of the second gate capacitor, coupling the first RF voltage to the gate of the second cascode transistor; based on the connecting of the second gate capacitor, further coupling an RF voltage at a source of the second cascode transistor to the gate of the second cascode transistor; and based on the further coupling, obtaining a second RF voltage at the gate of the second cascode transistor. - View Dependent Claims (19, 20)
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Specification