Positive logic digitally tunable capacitor

• US 9,948,281 B2
• Filed: 09/02/2016
• Issued: 04/17/2018
• Est. Priority Date: 09/02/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio
• Primary Examiner(s): CHEN, PATRICK C
• Application Number:
  US15/256,453
• Publication Number:
  US 20180069530A1
• Time in Patent Office: 592 Days
• Field of Search: 327109
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03J 3/16 Tuning without displacement of reactive element, e.g. by varying permeability
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03J 5/24 with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Claims

1. An integrated circuit block comprising:

a first node;

a second node;

a resistive network;

a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node; and

supply rails providing a first supply voltage and a second supply voltage;

wherein;

a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;

the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;

each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;

the resistive network comprises a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches;

the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable or disable the FET switches and thereby adjusting the capacitance between the two nodes;

the second supply voltage is a constant mid-rail voltage based on a threshold voltage of the plurality of FET switches; and

the first supply voltage and the second supply voltage are independent of a number of FET switches of the plurality of the FET switches.

2. The integrated circuit block of claim 1, wherein the resistive network comprises a plurality of resistors, the plurality of resistors having first terminals connected to drains of corresponding FET switches and second terminals connected to the second supply voltage;

the resistive network further comprising an end resistor, the end resistor connecting the source of the second end FET switch to the second supply voltage.

3. The integrated circuit block of claim 2, wherein the plurality of resistors has same resistances.

4. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 3, wherein the plurality of integrated circuits are configured in parallel.

5. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 2, wherein the plurality of integrated circuits are configured in parallel.

6. The integrated circuit block of claim 1, wherein the plurality of FET switches comprises two or more FET switches configured to withstand a voltage greater than a voltage withstood by one switch.

7. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 6, wherein the plurality of integrated circuits are configured in parallel.

8. The integrated circuit block of claim 1, wherein the two or more capacitors have same capacitances.

9. The integrated circuit block of claim 1, wherein the first supply voltage and the second supply voltage are configured to provide a maximum allowable voltage level across gate-source terminals of the FET switches.

10. A digitally tunable capacitor circuit comprising:

a plurality of integrated circuit blocks of claim 1, wherein the plurality of integrated circuits are configured in parallel.

11. The integrated circuit block of claim 1, further comprising a resistive path connecting the second supply voltage to a source of the second end FET switch.

12. A method of digitally tuning a capacitor in an integrated circuit, the method comprising the steps of:

providing a first node;

providing a second node;

providing a series arrangement of two or more capacitors and a plurality of FET switches;

the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;

providing a non-negative second supply voltage via a constant mid-rail voltage based on a threshold voltage of the plurality of FET switches, wherein the non-negative second supply voltage is independent of a number of FET switches of the plurality of FET switches;

providing a resistive network, the resistive network comprising;

a plurality of resistive paths connecting the second supply voltage to drains of corresponding FET switches of the plurality of FET switches;

a resistive path connecting the second supply voltage to a source of the second end FET switch;

providing a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches;

connecting each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;

coupling the series arrangement of two or more capacitors and the plurality of FET switches between the first node and the second node;

coupling a first capacitor of the two or more capacitors to the first node and coupling a second capacitor of the two or more capacitors to the second node; and

enabling or disabling the FET switches using the first supply voltage and the second supply voltage and thereby adjusting the capacitance between the two nodes.