Three phase and polarity encoded serial interface

• US 9,948,485 B2
• Filed: 02/02/2016
• Issued: 04/17/2018
• Est. Priority Date: 03/02/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wiley, George Alan
• Primary Examiner(s): Perez, James M
• Application Number:
  US15/013,003
• Publication Number:
  US 20160156457A1
• Time in Patent Office: 805 Days
• Field of Search: 375259-264, 375284-288, 375290-293, 341 50, 341 58, 341 68- 70
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Claims

1. A method for encoding data, comprising:

mapping a first number of bits of data to a sequence of transitions, wherein the sequence of transitions defines a second number of state transitions on a plurality of wires in a communications link; and

transmitting signals on the plurality of wires, wherein the signals are responsive to the sequence of transitions,

wherein the first number and the second number have different integer values,

wherein each transition encodes a non-integer number of data bits, and

wherein the plurality of wires comprise three wires.

2. The method of claim 1, wherein each transition in the sequence of transitions encodes a non-integer number of the data bits.

3. The method of claim 1, wherein the state of at least one of the plurality of wires changes at each transition.

4. The method of claim 1, wherein at least 6 states are defined for the plurality of wires.

5. The method of claim 1, further comprising:

embedding timing information in the sequence of transitions such that each transition encodes clock information.

6. The method of claim 5, wherein embedding the timing information in the sequence of transitions comprises:

determining a current state of the plurality of wires; and

providing a transition that causes the state of at least one of the plurality of wires to change between the current state of the plurality of wires and a next state of the plurality of wires,

wherein the next state is selected based on a value of data to be encoded in the transition from the current state of the plurality of wires.

7. An apparatus that encodes data, comprising:

a processing system configured to;

map a first number of bits of data to a sequence of transitions, wherein the sequence of transitions defines a second number of state transitions on a plurality of wires in a communications link; and

transmit signals on the plurality of wires, wherein the signals are responsive to the sequence of transitions,

wherein the first number and the second number have different integer values,

wherein each transition encodes a non-integer number of data bits, and

wherein the plurality of wires comprise three wires.

8. The apparatus of claim 7, wherein each transition in the sequence of transitions encodes a non-integer number of the data bits.

9. The apparatus of claim 7, wherein the state of at least one of the plurality of wires changes at each transition.

10. The apparatus of claim 7, wherein at least 6 states are defined for the plurality of wires.

11. The apparatus of claim 7, wherein the processing system is configured to:

embed timing information in the sequence of transitions such that each transition encodes clock information.

12. The apparatus of claim 11, wherein the processing system is configured to embed the timing information in the sequence of transitions by:

determining a current state of the plurality of wires; and

providing a transition that causes the state of at least one of the plurality of wires to change between the current state of the plurality of wires and a next state of the plurality of wires,

wherein the next state is selected based on a value of data to be encoded in the transition from the current state of the plurality of wires.

13. A method for decoding data, comprising:

receiving signals on a plurality of wires in a communications link;

determining a sequence of transitions in state of the plurality of wires; and

demapping a first number of bits of data from the sequence of transitions, wherein the sequence of transitions includes a second number of state transitions on the plurality of wires,

wherein the first number and the second number have different integer values,

wherein each transition encodes a non-integer number of data bits, and

wherein the plurality of wires comprise three wires.

14. The method of claim 13, wherein each transition in the sequence of transitions encodes a non-integer number of the data bits.

15. The method of claim 13, wherein the state of at least one of the plurality of wires changes at each transition.

16. The method of claim 13, wherein at least 6 states are defined for the plurality of wires.

17. The method of claim 13, further comprising:

extracting timing information from the sequence of transitions, wherein each transition encodes clock information.

18. The method of claim 17, wherein extracting the timing information in the sequence of transitions comprises:

determining a current state of the plurality of wires; and

determining a transition in the state of at least one of the plurality of wires between the current state of the plurality of wires and a next state of the plurality of wires.

19. An apparatus that decodes data, comprising:

a processing system configured to;

receive signals on a plurality of wires in a communications link;

determine a sequence of transitions in state of the plurality of wires; and

demap a first number of bits of data from the sequence of transitions, wherein the sequence of transitions includes a second number of state transitions on the plurality of wires,

wherein the first number and the second number have different integer values,

wherein each transition encodes a non-integer number of data bits, and

wherein the plurality of wires comprise three wires.

20. The apparatus of claim 19, wherein each transition in the sequence of transitions encodes a non-integer number of the data bits.

21. The apparatus of claim 19, wherein the state of at least one of the plurality of wires changes at each transition.

22. The apparatus of claim 19, wherein at least 6 states are defined for the plurality of wires.

23. The apparatus of claim 19, wherein the processing system is configured to:

extract timing information from the sequence of transitions, wherein each transition encodes clock information.

24. The apparatus of claim 23, wherein the processing system is configured to extract the timing information in the sequence of transitions by:

determining a current state of the plurality of wires; and

determining a transition in the state of at least one of the plurality of wires between the current state of the plurality of wires and a next state of the plurality of wires.