Abnormal clock rate detection in imaging sensor arrays

• US 9,948,878 B2
• Filed: 12/07/2015
• Issued: 04/17/2018
• Est. Priority Date: 04/23/2010
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Simolon, Brian, Kurth, Eric A., Goodland, Jim, Nussmeier, Mark, Hogasten, Nicholas, Hoelter, Theodore R., Strandemar, Katrin, Boulanger, Pierre, Sharp, Barbara, Aziz, Naseem Y.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Stewart, Kevin
• Application Number:
  US14/961,829
• Publication Number:
  US 20160224055A1
• Time in Patent Office: 862 Days
• Field of Search: None
• CPC Class Codes: G01R 23/00 Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: H04N 23/57 Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Claims

1. A device comprising:

a counter configured to receive a clock signal and adjust a count value in response to the clock signal;

a ramp generator configured to generate a ramp signal;

a first comparator configured to receive a reference signal via a first input and the ramp signal via a second input, and select a first count value of the counter at a first time in response to the reference signal and the ramp signal;

a temperature sensor configured to detect a temperature associated with the device and provide a temperature-dependent analog signal;

a second comparator configured to receive the temperature-dependent analog signal and the ramp signal, and select a second count value of the counter at a second time in response to the temperature-dependent analog signal and the ramp signal; and

a processor configured to determine a predetermined range for the detected temperature based on the second count value such that a maximum of the predetermined range used by the processor decreases as a frequency of the clock signal increases, and determine if the frequency of the clock signal is within a specified range based on whether the first count value is within the predetermined range for the detected temperature.

2. The device of claim 1, wherein the reference signal and the ramp signal received at the first comparator exhibit similar variations over temperature such that the first count value selected by the first comparator is substantially stable over temperature for a given frequency of the clock signal.

3. The device of claim 2, further comprising:

a reference signal generator configured to generate the reference signal that is independent of the clock signal;

a first analog component provided in a signal path between the reference signal generator and the first input of the first comparator to pass and/or adjust the reference signal to the first comparator; and

a second analog component provided in a signal path between the ramp generator and the second input of the first comparator to pass and/or adjust the ramp signal to the first comparator,

wherein the first and the second analog components are matched with respect to temperature-dependent variations to provide the reference signal and the ramp signal that exhibit similar temperature-dependent variations.

4. The device of claim 3, wherein the first and the second analog components comprise a matched pair of first and second buffers.

5. The device of claim 4, wherein the first and the second buffers are level shift buffers.

11. The device of claim 1, wherein:

the ramp signal ramps up or down with a rate of change independent of the clock signal; and

the first comparator is configured to select the first count value of the counter in response to the ramp signal reaching a substantially same level as the reference signal.

12. The device of claim 1, further comprising an infrared imaging sensor array configured to receive the clock signal, wherein the infrared imaging sensor array is configured to provide infrared images at a frame rate dependent on the frequency of the clock signal.

13. The device of claim 12, wherein the processor is configured to reduce the frame rate, drop image frames, and/or disable at least a portion of the device if the frequency of the clock signal is outside the specified range.

6. A method comprising:

adjusting a count value in response to a clock signal, wherein the clock signal is provided to a device;

generating a ramp signal;

comparing the ramp signal with a reference signal;

selecting a first count value of the count value at a first time in response to the comparing of the ramp signal with the reference signal; and

detecting a temperature associated with the device;

providing a temperature-dependent analog signal indicative of the temperature associated with the device;

comparing the ramp signal with the temperature-dependent analog signal;

selecting a second count value of the count value at a second time in response to the comparing of the ramp signal with the temperature-dependent analog signal;

determining a predetermined range for the detected temperature based on the second count value such that a maximum of the predetermined range for the detected temperature decreases as a frequency of the clock signal increases; and

determining if the frequency of the clock signal is within a specified range based on whether the first count value is within the predetermined range for the detected temperature.

7. The method of claim 6, wherein the reference signal and the ramp signal exhibit similar variations over temperature such that the selecting of the first count value is substantially stable over temperature for a given frequency of the clock signal.

8. The method of claim 7, further comprising:

passing and/or adjusting the reference signal by a first analog component prior to the selecting of the first count value; and

passing and/or adjusting the ramp signal by a second analog component prior to the selecting of the first count value,

wherein the first and the second analog components are provided as a matched pair configured to exhibit similar temperature-dependent variations in the reference signal and the ramp signal.

9. The method of claim 8, wherein:

the matched pair comprises a matched pair of first and second buffers;

the passing and/or adjusting of the reference signal comprises buffering the reference signal by the first buffer; and

the passing and/or adjusting of the ramp signal comprises buffering the ramp signal by the second buffer.

10. The method of claim 9, wherein:

the first and the second buffers are level shift buffers;

the buffering of the reference signal comprises shifting the reference signal by a predetermined level; and

the buffering of the ramp signal comprises shifting the ramp signal by the predetermined level.

14. The method of claim 6, wherein:

the ramp signal ramps up or down with a rate of change independent of the clock signal; and

the selecting of the first count value in response to the comparing of the ramp signal with the reference signal comprises selecting the first count value in response to the ramp signal reaching a substantially same level as the reference signal.

15. The method of claim 6, further comprising:

receiving, by an infrared imaging sensor array, the clock signal; and

providing, by the infrared imaging sensor array, infrared images at a frame rate dependent on the frequency of the clock signal.

16. The method of claim 15, further comprising performing a corrective action to reduce the frame rate, drop image frames, and/or disable at least a portion of the infrared imaging sensor array if the frequency of the clock signal is outside the specified range.