Combined analog architecture and functionality in a mixed-signal array

• US 9,952,282 B1
• Filed: 09/21/2015
• Issued: 04/24/2018
• Est. Priority Date: 05/05/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kutz, Harold M., Williams, Timothy John, Sullam, Bert S., Snyder, Warren S., Shutt, James H., Byrkett, Bruce E., Mar, Monte, Thiagarajan, Eashwar, Kohagen, Nathan Wayne, Wright, David G., Hastings, Mark E, Seguine, Dennis R.
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US14/860,515
• Time in Patent Office: 946 Days
• Field of Search: None
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

Claims

1. A programmable device, comprising:

a plurality of programmable blocks;

a debug interface coupled with the plurality of programmable blocks; and

a power manager coupled with the plurality of programmable blocks, wherein the power manager is configured to, based on a value of a register in a power subsystem, supply a first power level to a subset of the plurality of programmable blocks during debugging of the subset while supplying to a different subset of the plurality of programmable blocks a second power level different from the first power level.

2. The programmable device of claim 1, wherein the plurality of programmable blocks comprises a plurality of reconfigurable analog blocks and a plurality of reconfigurable digital blocks.

3. The programmable device of claim 1, further comprising a plurality of power domains, wherein each of the plurality of power domains includes one or more of the plurality of programmable blocks.

4. The programmable device of claim 3, wherein the power manager is coupled with each of the plurality of power domains and is configurable to supply a different power level to each of the plurality of power domains.

5. The programmable device of claim 4, wherein the power manager is configured to wake each of the plurality of power domains from a lower power mode to a higher power mode in response to a wake signal.

6. The programmable device of claim 3, further comprising a debug on-chip (DoC) module, wherein the DoC module is configured to override control of the programmable device by the processor in response to one or more debug commands received from an external device connected to the debug interface.

7. The programmable device of claim 6, further comprising a processor, wherein one of the plurality of power domains includes the DoC module, the processor, and the power manager.

8. A method of operating a programmable device, comprising:

configuring one or more of a plurality of programmable blocks to perform one of a plurality of functions in a programmable device;

initiating a debugging mode of the programmable device in response to an input received at a debug interface of the programmable device; and

according to a value of a register in a power subsystem, supplying power to a subset of the plurality of programmable blocks while operating the programmable device in the debugging mode while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

9. The method of claim 8, wherein configuring one or more of the plurality of programmable blocks further comprises reconfiguring one or more analog blocks and reconfiguring one or more digital blocks, wherein the plurality of programmable blocks comprises the one or more analog blocks and the one or more digital blocks.

10. The method of claim 8, further comprising supplying a different power level from a power manager of the programmable device to each of a plurality of power domains each including one or more of the plurality of programmable blocks.

11. The method of claim 10, further comprising:

receiving a wake signal at a debug interface of the programmable device; and

waking each of the plurality of power domains from a lower power mode to a higher power mode in response to the wake signal.

12. The method of claim 10, further comprising overriding control of the programmable device by the processor in response to one or more debug commands received at a debug on-chip (DoC) module from an external device connected to the debug interface.

13. A system, comprising:

a processor;

a plurality of programmable blocks coupled with the processor;

a debug interface coupled with the plurality of programmable blocks;

a debug on-chip (DoC) module coupled with the debug interface;

a power manager coupled with the plurality of programmable blocks, wherein the power manager is configured to, based on a value of a register in a power subsystem, supply a first power level to a subset of the plurality of programmable blocks during debugging of the subset while supplying to a different subset of the plurality of programmable blocks a second power level different from the first power level.

14. The system of claim 13, further comprising an external debug device coupled with the debug interface and configured to supply one or more debugging signals to the DoC module via the debug interface.

15. The system of claim 14, wherein the DoC module is configured to override the processor in response to one or more debug commands received from an external debug device connected to the debug interface.

16. The system of claim 13, wherein the plurality of programmable blocks comprises a plurality of reconfigurable analog blocks and a plurality of reconfigurable digital blocks.

17. The system of claim 13, further comprising a plurality of power domains, wherein each of the plurality of power domains includes one or more of the plurality of programmable blocks.

18. The system of claim 17, wherein the power manager is configurable to supply a different power level to each of the plurality of power domains.

19. The system of claim 17, wherein the power manager is configured to wake each of the plurality of power domains from a lower power mode to a higher power mode in response to a wake signal.

20. The system of claim 17, wherein one of the plurality of power domains includes the DoC module, the processor, and the power manager.