Compressed scan chains with three input mask gates and registers

• US 9,952,283 B2
• Filed: 11/18/2015
• Issued: 04/24/2018
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Parekhji, Rubin A., Jain, Arvind, Subramanian, Sundarrajan
• Primary Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US14/944,971
• Publication Number:
  US 20160069958A1
• Time in Patent Office: 888 Days
• Field of Search: 714729
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claims

1. An electronic scan circuitry comprising:

(a) decompressor circuitry having a serial data input line and parallel data output lines;

(b) a first scan chain having a first scan chain input connected to one parallel data output line and having a first scan chain output;

(c) masking circuitry having a first masking input connected to the first scan chain output, the masking circuitry including;

(i) a first gate having a first input connected to the first masking input, a second input coupled to a qualify line, a third input, and a first masking output; and

(ii) a first register having a serial input and an output connected to the third input; and

(d) compactor circuitry having a first parallel compactor input connected to the first masking output and a serial compactor output.

2. The electronic scan circuitry of claim 1 including:

(a) a second scan chain having a second scan chain input connected to another parallel data output line and having a second scan chain output;

(b) the masking circuitry including a second masking input connected to the second scan chain output, the masking circuitry including;

(i) a second gate having a first input connected to the second masking input, a second input coupled to another qualify line, a third input, and a second masking output; and

(ii) a second register having a serial input, a serial output coupled to the serial input of the first register, and an output connected to the third input; and

(c) compactor circuitry including a second parallel compactor input connected to the second masking output.

3. The electronic scan circuitry of claim 2 including scannable masking qualification circuit having a serial output coupled to the serial input of the second register and having a qualify line coupled to the second inputs of the first and second gates.

4. The electronic scan circuitry of claim 3 in which the scannable masking qualification circuit includes a chain shift register having a serial input, a serial output coupled with the serial input of the second register, and a set of shift register cells coupled between the serial input and serial output.

5. The electronic scan circuitry of claim 2 including scan circuitry having a clock signal input and a scan output coupled to the first and second scan chains.

6. The electronic scan circuitry of claim 2 in which the scannable masking qualification circuit includes multiplexer circuitry having a qualify line coupled to the second inputs of the first and second gates, having a control input, and including generator circuitry having an output coupled to the control input of the multiplexer circuitry.