Device power management state transition latency advertisement for faster boot time

• US 9,952,643 B2
• Filed: 12/31/2015
• Issued: 04/24/2018
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wagh, Mahesh, Looi, Lily Pao
• Primary Examiner(s): Chen, Xuxing
• Application Number:
  US14/986,573
• Publication Number:
  US 20160110309A1
• Time in Patent Office: 845 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

Claims

1. A apparatus comprising:

a serial point-to-point link interface to enable communication between a processor and a device;

wherein the serial point-to-point link interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize a serial stream from the device;

wherein the protocol stack is to support a plurality of power management states, including an active state, a first off state, in which one or more power rails are on, and a second off state, in which the one or more power rails are off;

wherein the protocol stack is configured to provide a default wait time to allow the device to begin a transition from the second off state to the active state prior to access of the device; and

wherein the protocol stack, in response to an indication the device is ready to enter the active state, is to access the device prior to expiration of the default wait time to complete the transition.

2. The apparatus of claim 1, wherein the apparatus is a system on a chip.

3. The apparatus of claim 1, wherein the protocol stack is a peripheral component interconnect express (PCIe) protocol stack and the device is a PCIe endpoint device.

4. The apparatus of claim 1, wherein the first off state is a D3_hot state and the second off state is a D3_cold state.

5. A apparatus comprising:

a multicore processor;

a level-2 (L2) cache controller coupled to the multicore processor;

an L2 cache coupled to the L2 cache controller and the multicore processor;

an integrated memory controller; and

a serial point-to-point link interface to enable communication between the multicore processor and a device;

wherein the serial point-to-point link interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize a serial stream from the device;

wherein the protocol stack is to support a plurality of power management states, including an active state, a first off state, in which power rails are on, and a second off state, in which the power rails are off;

wherein the protocol stack is configured to provide a default wait time to allow the device to begin a transition from the second off state to the active state prior to access of the device; and

wherein the protocol stack, in response to an indication the device is ready to enter the active state, is to access the device prior to expiration of the default wait time to complete the transition.

6. The apparatus of claim 5, wherein the apparatus is a system on a chip.

7. The apparatus of claim 5, wherein the protocol stack is a peripheral component interconnect express (PCIe) protocol stack and the device is a PCIe endpoint device.

8. The apparatus of claim 5, wherein the first off state is a D3_hot state and the second off state is a D3_cold state.