Centralized synchronization mechanism for a multi-core processor

• US 9,952,654 B2
• Filed: 01/13/2016
• Issued: 04/24/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): STEWART, KEVIN MICHAEL
• Application Number:
  US14/994,544
• Publication Number:
  US 20160162017A1
• Time in Patent Office: 832 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core'"'"'s target operating state.

Claims

1. A multi-core microprocessor that supports a plurality of operating states representing different levels of performance and power consumption, the microprocessor comprising:

a plurality of cores;

a control unit configured to put selected cores into selected operating states at selected times; and

for each core, a synchronization register external to that core, specific to that core, and readable by the control unit;

wherein each core is configured to respond to an instruction to target an operating state by writing a value identifying the target operating state to its synchronization register;

wherein the control unit is configured to help the cores work cooperatively to cause a power saving action that affects a shared resource provided that the action does not reduce performance of any core sharing that resource below its target operating state;

wherein the control unit is configured to refrain from performing a power-saving action that affects a shared resource until all of the cores sharing that resource have written values identifying a consistent target operating state to their synchronization registers, wherein a core'"'"'s target operating state is consistent with the power saving action if the power saving action would not reduce performance of the core below its target operating state;

wherein the control unit is configured to cause individual cores to enter a sleep state while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action;

wherein the control unit is configured to wake only a selected one of the cores sharing the shared resource, when all cores sharing that resource have written values identifying target operating states that are consistent with the power-saving action; and

wherein in response to being awaken, the selected core communicates with a chipset to disable the shared resource.

2. The microprocessor of claim 1, wherein the control unit is configured to implement at least one operating state by removing power from a selected one or more cores.

3. The microprocessor of claim 1, wherein the control unit is configured to help the cores work cooperatively to cause at least one operating state to be implemented by writing back and invalidating local cache memories of selected cores.

4. The microprocessor of claim 1, wherein the control unit is configured to help the cores work cooperatively to cause a core to prepare for at least one operating state by saving the state of the core to an external memory.

5. The microprocessor of claim 1, wherein in response to a determination that all of the cores sharing a resource have written values identifying target operating states that are consistent with performing a power saving action affecting a shared resource, the control unit helps the cores work cooperatively to cause the power saving action, wherein a core'"'"'s target operating state is consistent with the power saving action if the power saving action would not reduce performance of the core below its target operating state.

6. The microprocessor of claim 1, wherein the selected one of the cores comprises a last core that wrote the value identifying the consistent target operating state to its synchronization register.

7. The microprocessor of claim 1, wherein the control unit is configured to cause individual cores to enter an alternative power-saving operating state that does not affect the shared resource while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action.

8. The microprocessor of claim 1, wherein the control unit is configured to read the target operating states from each core-specific synchronization register and write a composite target operating state value equal to a least restrictive one of the target operating states stored in the core-specific synchronization registers, wherein the least restrictive target operating state is one that would reduce performance of a core the least.

18. The microprocessor of claim 1, wherein:

each synchronization register includes a wakeup events field;

each core is configured to identify a wakeup event; and

the control unit is configured to wakeup a core if the core identified a wakeup event and the wakeup event identified by the core occurs.

19. The microprocessor of claim 18, wherein one of the one or more wakeup events is that all of the cores are synchronized.

9. A method of managing power consumption in a multi-core microprocessor that supports a plurality of operating states representing different levels of performance and power consumption, the method comprising:

issuing an instruction to each core of the microprocessor to target an operating state, so that different cores have different target operating states;

each core that receives the instruction writing a value identifying the targeted operating state to a core-specific synchronization register external to the core, wherein each core has a synchronization register specific to that core; and

a control unit reading the core-specific synchronization registers and comparing their values to identify a maximum extent to which each core'"'"'s targeted operating states can be implemented without reducing performance of any other core below its own target operating state;

implementing each core'"'"'s targeted operating state to the identified maximum extent, so that the implementation does not reduce performance of any other core below its own target operating state;

the control unit refraining from performing a power-saving action that affects a shared resource until all of the cores sharing that resource have written values identifying a target operating state consistent with the power-saving action to their synchronization registers, wherein a core'"'"'s target operating state is consistent with the power saving action if the power saving action would not reduce performance of the core below its target operating state;

causing at least one of the cores sharing the resource to enter a sleep state while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action;

waking only a selected one of the cores sharing the resource, when all cores sharing the resource have written values identifying target operating states that are consistent with the power-saving action; and

the selected core communicating with a chipset to disable the shared resource.

10. The method of claim 9, wherein implementing the targeted operating states of the microprocessor'"'"'s cores comprise removing power from at least one core while maintaining power for at least one other core.

11. The method of claim 9, wherein for at least one of the cores, implementing the targeted operating state to the identified maximum extent includes writing back and invalidating local cache memories of selected cores.

12. The method of claim 9, further comprising preparing at least one of the cores for an operating state by saving the state of the core to an external memory.

13. The method of claim 9, wherein at least one of the targeted operating states specifies a setting that would restrict a resource shared by two or more cores, the method further comprising:

the control unit determining whether any of the cores sharing the resource have written values identifying target operating states that specify a less restrictive setting for the shared resource;

when none of the cores sharing the resource have written values identifying target operating states that specify a less restrictive setting for the shared resource, the control unit helping the cores work cooperatively to implement the setting.

14. The method of claim 9, wherein the selected one of the cores comprises a last core that wrote the value identifying the consistent target operating state to its synchronization register.

15. The method of claim 9, further comprising causing at least one core sharing the resource to enter an alternative operating state to its target operating state, wherein the alternative operating state does not affect the shared resource, while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action.

16. The method of claim 9, further comprising the control unit reading the target operating states from each core-specific synchronization register and writing a composite target operating state value equal to a least restrictive one of the target operating states stored in the core-specific synchronization registers, wherein the least restrictive target operating state is one that would reduce performance of a core the least.

20. The method of claim 9, wherein each synchronization register includes a wakeup events field, the method further comprising:

each core writing another value identifying a wakeup event to the core'"'"'s synchronization register; and

the control unit waking up a core if the core identified a wakeup event and the wakeup event identified by the core occurs.

21. The method of claim 20, wherein one of the one or more wakeup events is that all of the cores are synchronized.

17. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor that supports a plurality of operating states representing different levels of performance and power consumption, the computer usable program code comprising;

first program code for specifying a control unit, configured to put selected cores into selected operating states at selected times; and

second program code for specifying, for each core, a synchronization register external to that core, specific to that core, and readable by the control unit;

wherein each core is configured to respond to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register; and

wherein the control unit is configured to help the cores work cooperatively to cause a power saving action that affects a shared resource provided that the action does not reduce performance of any core sharing that resource below the core'"'"'s target operating state;

wherein the control unit is configured to refrain from performing a power-saving action that affects a shared resource until all of the cores sharing that resource have written values identifying a consistent target operating state to their synchronization registers, wherein a core'"'"'s target operating state is consistent with the power saving action if the power saving action would not reduce performance of the core below its target operating state;

wherein the control unit is configured to cause individual cores to enter a sleep state while waiting for other cores sharing the resource to write values identifying target operating states that are consistent with the power-saving action;

wherein the control unit is configured to wake only a selected one of the cores sharing the shared resource, when all cores sharing that resource have written values identifying target operating states that are consistent with the power-saving action; and

wherein in response to being awaken, the selected core communicates with a chipset to disable the shared resource.