Dynamic memory management for a virtual supercomputer

• US 9,952,860 B2
• Filed: 03/12/2014
• Issued: 04/24/2018
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Veriscape, Inc.
• Original Assignee: Veriscape, Inc.
• Inventors: Berkowitz, Gary C., Wurtz, Charles
• Primary Examiner(s): Johnson, Cedric D
• Application Number:
  US14/206,035
• Publication Number:
  US 20140278340A1
• Time in Patent Office: 1,504 Days
• Field of Search: None
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/45541 Bare-metal, i.e. hypervisor runs directly on hardware

Abstract

Present invention embodiments enable the handling of various index-memory architectures for a virtual supercomputer that would allow for a heterogeneous storage of variable length index words with non-sequential addressing, and also dynamic changes to the index-memory architecture. A computer-implemented system, method, and apparatus allow for different types of node index memory (NIM) architectures for the virtual supercomputer. The first type allows for homogenous NIM segments, and implementing sequential node-number addressing. A second type of architecture allows for heterogeneous IW configurations (variable length and field structure), but sill uses sequential node-number addressing. A third type allows for non-sequential node-number addressing, but still uses homogeneous IW configurations. To implement this, a new virtual hardware element is required, an Index-Word Address Table. The fourth type of architecture is a fully variable random-access architecture, whereby index-words are not sequential, nor are they identically configured. This also requires the Index-Word Address Table.

Claims

1. A system to manage memory comprising:

a computer system, including at least one processor and an operating system to control operation of said computer system, to dynamically configure and emulate a hardware architecture of a processing system that processes one or more nodes to determine a solution for a problem, wherein at least one of said nodes includes data for said problem and said computer system further includes;

a virtual machine unit to emulate said hardware architecture and manage said nodes within a solution space, wherein said hardware architecture is designed to process said nodes;

a virtual operating system to configure said virtual machine unit and to control operation of said virtual machine unit to emulate said hardware architecture based on parameters, wherein said virtual machine unit includes;

a plurality of node modules to manage the one or more nodes;

a node index memory including a plurality of memory segments storing one or more index words each indicating a configuration for an associated node; and

an index memory module to dynamically reconfigure an architecture of the node index memory, wherein each memory segment of the node index memory implements a dynamically specifiable memory architecture and at least two different memory segments enable different memory architectures, wherein the memory architectures include an architecture storing index words of variable length in a non-sequential order of node identifiers within a segment, and wherein the node index memory includes a structure including a node identifier and an address of a corresponding index word in a segment for accessing the index words stored in the non-sequential order of node identifiers.

2. The system of claim 1, wherein the emulated hardware architecture includes an instruction set, and operates on the at least one processor.

3. The system of claim 1, wherein the emulated processing system includes a distributed network of processing elements each employing the emulated hardware architecture.

4. The system of claim 1, wherein at least one node is associated with an index word and a data word.

5. The system of claim 1, wherein each node represents one or more data structures selected from a group of:

numeric tags, character tags, Boolean flags, numeric values, character values, object IDs, database-record IDs, simple arrays, variable-density multidimensional arrays, symbolic functions, mathematical functions, connection pointers to other nodes, function pointers, lookup-table list pointers, linked-lists, and pointers to other solution spaces or data representations.

6. The system of claim 1, wherein the one or more nodes include a plurality of nodes that are interconnected in one or more topologies selected from a group of:

independent point-clouds, ordered sets of points, acyclic graphs, cyclic graphs, balanced trees, recombining graphs, meshes, lattices, and combinations thereof.

7. The system of claim 1, wherein the virtual machine unit includes:

a first virtual unit to configure nodes and the emulated hardware architecture, including register structures, node data structures, arithmetic modes, and memory schemes;

a second virtual unit to create nodes, compute results for nodes, navigate nodes, and alter nodes and interconnections;

a third virtual unit to provide function evaluation and fixed-point integer arithmetic with application-selectable precision; and

a fourth virtual unit to manage distribution of data and processes and dynamically reconfigure an architecture of the node index memory.

8. A method for managing memory comprising:

dynamically configuring and emulating, via a computer system including at least one processor and an operating system to control operation of said computer system, a hardware architecture of a processing system that processes one or more nodes to determine a solution for a problem, wherein at least one of said nodes includes data for said problem;

configuring and controlling emulation of said hardware architecture based on parameters, wherein said configuring and controlling further includes;

managing the one or more nodes; and

dynamically reconfiguring an architecture of a node index memory including a plurality of memory segments storing one or more index words each indicating a configuration for an associated node, wherein each memory segment of the node index memory implements a dynamically specifiable memory architecture and at least two different memory segments enable different memory architectures, wherein the memory architectures include an architecture storing index words of variable length in a non-sequential order of node identifiers within a segment, and wherein the node index memory includes a structure including a node identifier and an address of a corresponding index word in a segment for accessing the index words stored in the non-sequential order of node identifiers.

9. The method of claim 8, wherein the emulated hardware architecture includes an instruction set, and operates on the at least one processor.

10. The method of claim 8, wherein the emulated processing system includes a distributed network of processing elements each employing the emulated hardware architecture.

11. The method of claim 8, wherein at least one node is associated with an index word and a data word.

12. The method of claim 8, wherein each node represents one or more data structures selected from a group of:

numeric tags, character tags, Boolean flags, numeric values, character values, object IDs, database-record IDs, simple arrays, variable-density multidimensional arrays, symbolic functions, mathematical functions, connection pointers to other nodes, function pointers, lookup-table list pointers, linked-lists, and pointers to other solution spaces or data representations.

13. The method of claim 8, wherein the one or more nodes include a plurality of nodes that are interconnected in one or more topologies selected from a group of:

independent point-clouds, ordered sets of points, acyclic graphs, cyclic graphs, balanced trees, recombining graphs, meshes, lattices, and combinations thereof.

14. The method of claim 8, wherein the configuring and controlling further includes:

configuring nodes and the emulated hardware architecture, including register structures, node data structures, arithmetic modes, and memory schemes;

creating nodes, computing results for nodes, navigating nodes, and altering nodes and interconnections;

providing function evaluation and fixed-point integer arithmetic with application-selectable precision; and

managing distribution of data and processes and dynamically reconfiguring an architecture of the node index memory.