Method, apparatus and instructions for parallel data conversions
First Claim
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1. A processor comprising:
- a register file including a first packed data register and a second packed data register;
register renaming circuitry to perform renaming of physical registers within the register file;
a decoder to decode an instruction;
scheduling circuitry to queue operations corresponding to the instruction for execution; and
execution circuitry to execute the operations corresponding to the instruction to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register,each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits.
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Abstract
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
12 Citations
21 Claims
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1. A processor comprising:
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a register file including a first packed data register and a second packed data register; register renaming circuitry to perform renaming of physical registers within the register file; a decoder to decode an instruction; scheduling circuitry to queue operations corresponding to the instruction for execution; and execution circuitry to execute the operations corresponding to the instruction to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (2, 3, 4)
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5. A processor comprising:
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a register file including a first packed data register and a second packed data register; register renaming circuitry to perform renaming of physical registers within the register file; a decoder to decode an instruction, the instruction specifying one or more operations; scheduling circuitry to queue the one or more operations for execution; and execution circuitry to execute the one or more operations to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (6, 7, 8)
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9. A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
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renaming physical registers within a register file including a first packed data register and a second packed data register; decoding an instruction specifying one or more operations; scheduling the one or more operations for execution; and executing the one or more operations to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (10, 11, 12)
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13. An apparatus comprising:
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means for renaming physical registers within a register file including a first packed data register and a second packed data register; means for decoding an instruction specifying one or more operations; means for scheduling the one or more operations for execution; and means for executing the one or more operations to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (14, 15, 16)
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17. A system comprising:
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at least one processor; a system memory to store instructions to be processed by the at least one processor; a memory controller to communicatively couple the at least one processor to the system memory over a system memory bus; the at least one processor comprising; a register file including a first packed data register and a second packed data register; register renaming circuitry to perform renaming of physical registers within the register file; a decoder to decode an instruction, the instruction specifying one or more operations; scheduling circuitry to queue the one or more operations for execution; and execution circuitry to execute the one or more operations to convert a plurality of first packed floating point data elements from the first packed data register to a plurality of packed integer results, to truncate the packed integer results, and to store the packed integer results in the second packed data register, each of the first packed floating point data elements having a first number of bits, each of the packed integer results having a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (18, 19, 20, 21)
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Specification