Iterator register for structured memory

• US 9,952,972 B2
• Filed: 02/27/2017
• Issued: 04/24/2018
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheriton, David R., Firoozshahian, Amin, Solomatnikov, Alexandre Y.
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US15/443,907
• Publication Number:
  US 20170168938A1
• Time in Patent Office: 421 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.

Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.

Claims

1. An apparatus comprising:

a memory that is to store data in a pointer-linked data structure, the pointer-linked data structure including a plurality of nodes, wherein the memory comprises one or more of a content-addressable memory, a snapshot checkpointing memory, a database, a snapshot of state for lock-free execution type of memory, an inverted index memory, or a sparse matrix memory; and

a processor in communication with the memory, the processor including at least one iterator register, wherein the iterator register is to store a first pointer chain that specifies a location of a first data element within the pointer-linked data structure from a root node, of the plurality of nodes, to a leaf node, of the plurality of nodes, and

wherein when a subsequent access of data in the pointer-linked data structure causes a writing of a second pointer chain, associated with access of a second data element within the pointer-linked data structure, to the iterator register and the second pointer chain includes one or more same pointers as included in the first pointer chain, a first portion of the iterator register is to store only a portion of the second pointer chain not in common with the first pointer chain and a second portion of the iterator register is to retain the one or more same pointers as included in the first pointer chain.

2. The apparatus of claim 1, wherein the pointer-linked data structure included in the memory is organized in immutable memory blocks.

3. The apparatus of claim 1, wherein the processor is to remove duplicate data in the pointer-link data structure.

4. The apparatus of claim 1, wherein the iterator register is to simultaneously store a plurality of pointer chains.

5. The apparatus of claim 1, wherein the iterator register is to maintain a transient line state.

6. The apparatus of claim 1, wherein the processor, under execution of one or more instructions, is to activate or inactivate the iterator register.

7. The apparatus of claim 1, wherein the iterator register comprises storage that is more rapidly accessible than the memory.

8. The apparatus of claim 1, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first pointer is the same pointer included in both the first and second pointer chains.

9. The apparatus of claim 1, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the second pointer is the same pointer included in both the first and second pointer chains.

10. The apparatus of claim 1, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first and second pointers are the same pointers included in both the first and second pointer chains.

11. The apparatus of claim 1, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first pointer points to the root node.

12. A computer-implemented method comprising:

loading into a selected iterator register, from a memory that stores one or more pointer-linked data structures, at least first, second, and third pointers associated with a selected pointer-linked data structure, of the one or more pointer-linked data structures, wherein the first, second, and third pointers comprise a first pointer chain that specifies a location of a first data element within the selected pointer-linked data structure from a root node, of a plurality of nodes of the selected pointer-linked data structure, to a first leaf node, of the plurality of nodes; and

loading into the selected iterator register at least a portion of a second pointer chain having two or more pointers leading to a second data element located within a second leaf node of the selected pointer-linked data structure, wherein, when the second pointer chain includes one or more same pointers as included in the first pointer chain, loading into the selected iterator register only the portion of the second pointer chain not in common with the first pointer chain and retaining the one or more same pointers as included in the first pointer chain,

wherein the memory comprises one or more of a content-addressable memory, a snapshot checkpointing memory, a database, a snapshot of state for lock-free execution type of memory, an inverted index memory, or a sparse matrix memory.

13. The method of claim 12, wherein the pointer-linked data structure included in the memory is organized in immutable memory blocks.

14. The method of claim 12, wherein the selected iterator register is to simultaneously store a plurality of pointer chains.

15. The method of claim 12, wherein the selected iterator register is to maintain a transient line state.

16. The method of claim 12, comprising:

activating or inactivating the selected iterator register under execution of one or more instructions by a processor.

17. The method of claim 12, wherein the selected iterator register comprises storage that is more rapidly accessible than the memory.

18. The method of claim 12, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first pointer is the same pointer included in both the first and second pointer chains.

19. The method of claim 12, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the second pointer is the same pointer included in both the first and second pointer chains.

20. The method of claim 12, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first and second pointers are the same pointers included in both the first and second pointer chains.

21. The method of claim 12, wherein the first pointer chain includes at least first, second, and third pointers, the first pointer points to the second pointer and the second pointer points to the third pointer, and wherein the first pointer points to the root node.

22. One or more computer-readable storage media comprising a plurality of instructions to cause a processor, in response to execution by the processor, to:

load into an iterator register, from a memory that stores one or more pointer-linked data structures, at least first, second, and third pointers associated with a selected pointer-linked data structure, of the one or more pointer-linked data structures, wherein the first, second, and third pointers comprise a first pointer chain that specifies a location of a first data element within the selected pointer-linked data structure from a root node, of a plurality of nodes of the selected pointer-linked data structure, to a first leaf node, of the plurality of nodes, wherein the first, second, and third pointers are to be loaded into respective pointer fields included in the iterator register; and

load into the iterator register at least a portion of a second pointer chain having two or more pointers leading to a second data element located within a second leaf node of the selected pointer-linked data structure, wherein, when the second pointer chain includes one or more same pointers as included in the first pointer chain, load into the iterator register only the portion of the second pointer chain not in common with the first pointer chain and retain the one or more same pointers as included in the first pointer chain,

wherein the memory comprises one or more of a content-addressable memory, a snapshot checkpointing memory, a database, a snapshot of state for lock-free execution type of memory, an inverted index memory, or a sparse matrix memory.

23. The computer-readable storage media of claim 22, wherein the pointer-linked data structure included in the memory is organized in immutable memory blocks.

24. The computer-readable storage media of claim 22, wherein the iterator register is to maintain a transient line state.

25. The computer-readable storage media of claim 22, wherein the iterator register comprises storage that is more rapidly accessible than the memory.

26. The computer-readable storage media of claim 22, wherein the first pointer is the same pointer included in both the first and second pointer chains.

27. The computer-readable storage media of claim 22, wherein the second pointer is the same pointer included in both the first and second pointer chains.

28. The computer-readable storage media of claim 22, wherein the first and second pointers are the same pointers included in both the first and second pointer chains.