Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation

• US 9,952,991 B1
• Filed: 04/17/2015
• Issued: 04/24/2018
• Est. Priority Date: 04/17/2014
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Bruce, Ricardo H., Verdan, Marlon B., Jago-on, Rowenah Michelle
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US14/690,339
• Time in Patent Office: 1,103 Days
• Field of Search: 710 22- 24, 710 29
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

Claims

1. A method, comprising:

fetching, by a fetching module, a first set of descriptors from a memory device and writing, by the fetching module, the first set of descriptors to a buffer;

retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation;

checking, by the fetching module, if space is available in the buffer; and

if space is available in the buffer, fetching, by the fetching module, a second set of descriptors from the memory device and writing, by the fetching module, the second set of descriptors to the buffer during or after the processing of the first set of descriptors;

wherein the first set of descriptors are fetched from the memory device until an end-of-the-link information is detected in the first set.

2. The method of claim 1, further comprising:

writing the first set and second set of descriptors into the memory device prior to fetching the first set and the second set from the memory device.

3. The method of claim 1, further comprising:

segregating descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value;

wherein each descriptor queue group comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.

4. The method of claim 1, further comprising:

using a group link information to link a plurality of descriptor queue groups.

5. The method of claim 1, further comprising:

using a sequence information to categorize a plurality of descriptor queue groups into a plurality of descriptor links, wherein each descriptor link has a different corresponding priority value.

6. The method of claim 1, further comprising:

extracting descriptor queues in a plurality of descriptor queue groups and re-arranging the descriptor queues as a sequence before execution of the descriptor queues in respective channels.

7. The method of claim 1, further comprising:

processing at least one of the descriptors in a plurality of Direct Memory Access (DMA) engines.

8. The method of claim 1, comprising:

using a sequence link information in a descriptor queue group to link a plurality of descriptors.

9. An apparatus, comprising:

a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer;

a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation;

wherein the fetching module is configured to check if space is available in the buffer; and

wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors;

wherein the fetching module is configured to fetch the first set of descriptors from the memory device until an end-of-the-link information is detected in the first set.

10. The apparatus of claim 9, further comprising:

a processor configured to write the first set and second set of descriptors into the memory device prior to the fetching module fetching the first set and the second set from the memory device.

11. The apparatus of claim 9, wherein the sequencer is configured to segregate descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value;

wherein each descriptor queue group comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.

12. The apparatus of claim 9 wherein the sequencer is configured to use a group link information to link a plurality of descriptor queue groups.

13. The apparatus of claim 9, wherein the sequencer is configured to use a sequence information to categorize a plurality of descriptor queue groups into a plurality of descriptor links, wherein each descriptor link has a different corresponding priority value.

14. The apparatus of claim 9, wherein the sequencer is configured to extract descriptor queues in a plurality of descriptor queue groups and to re-arrange the descriptor queues as a sequence before execution of the descriptor queues in respective channels.

15. The apparatus of claim 9, wherein the sequencer comprises a plurality of sequencers, wherein each sequencer is in a different respective Direct Memory Access (DMA) engine, wherein each of the plurality of sequencers is configured to process at least one of the descriptors.

16. The apparatus of claim 9, wherein the sequencer comprises a plurality of sequencers, wherein the plurality of sequencers are configured to use a sequence link information in a descriptor queue group to link a plurality of descriptors.

17. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

fetching, by a fetching module, a first set of descriptors from a memory device and writing, by the fetching module, the first set of descriptors to a buffer;

retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation;

checking, by the fetching module, if space is available in the buffer; and

if space is available in the buffer, fetching, by the fetching module, a second set of descriptors from the memory device and writing, by the fetching module, the second set of descriptors to the buffer during or after the processing of the first set of descriptors;

segregating descriptor queue groups into a plurality of descriptor links in the buffer and wherein each of the descriptor links has a different corresponding priority value;

wherein each descriptor queue groups comprises a plurality of descriptor queues and wherein each descriptor queue comprises a plurality of descriptors.