Pseudo-dynamic circuit for multi-voltage timing interlocks

• US 9,953,687 B1
• Filed: 10/21/2016
• Issued: 04/24/2018
• Est. Priority Date: 10/21/2016
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wuu, John J., Freese, Ryan, Schreiber, Russell J.
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US15/299,709
• Publication Number:
  US 20180114555A1
• Time in Patent Office: 550 Days
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.

Claims

1. An apparatus comprising:

an interlock circuit coupled to receive a first input signal from a first voltage domain and a second input signal from a second voltage domain, the interlock circuit including,

a keeper circuit having a pull-up portion coupled to the second input signal and configured to maintain an output signal on an output node of the interlock circuit at a first high voltage level associated with the first voltage domain until the first input signal is at the first high voltage level and the second input signal is at a second high voltage level associated with the second voltage domain; and

a pull-down circuit coupled to receive the first input signal and the second input signal, wherein the keeper circuit is configured to be weaker than the pull-down circuit, to thereby cause the output node to transition from the first high voltage level to a low voltage level responsive to the second input signal transitioning to the second high voltage level from the low voltage level while the first input signal is at the first high voltage level.

2. The apparatus as recited in claim 1, wherein the pull-up portion of the keeper circuit comprises:

first and second transistors serially coupled between the output node of the interlock circuit and a power supply node of the first voltage domain.

3. The apparatus as recited in claim 2,

wherein the first transistor is coupled to receive an inverted version of the output signal as a first transistor gate signal;

and

wherein the second transistor is coupled to receive the second input signal as a second transistor gate signal.

4. The apparatus as recited in claim 1,

wherein the second input signal decouples the pull-up portion of the keeper circuit in response to the second input signal transitioning to the first high voltage level from the low voltage level.

5. The apparatus as recited in claim 1, wherein the first high voltage level associated with the first voltage domain is a different voltage level than the second high voltage level associated with the second voltage domain.

6. The apparatus as recited in claim 2, wherein the pull-down circuit comprises:

a third and a fourth transistor serially coupled between the output node and a ground node;

the third transistor coupled to receive the first input signal as a third transistor gate signal; and

the fourth transistor coupled to receive the second input signal as a fourth transistor gate signal.

7. The apparatus as recited in claim 1, wherein,

the keeper circuit is configured to be weaker than the pull-down circuit, to thereby cause the output node to transition from the first high voltage level to the low voltage level responsive to the first input signal transitioning to the first high voltage level from the low voltage level while the second input signal is at the second high voltage level.

8. The apparatus as recited in claim 1, wherein the keeper circuit further comprises a pull-down portion coupled to the first input signal and the pull-down portion is coupled to an inverted version of the output signal.

9. The apparatus as recited in claim 6, wherein the interlock circuit further comprises a fifth transistor coupled between the output node and the power supply node as a pull-up transistor, the fifth transistor coupled to receive the first input signal as a fifth transistor gate signal, wherein the fifth transistor causes the output node to go to the first high voltage level responsive to the first input signal being at the low voltage level.

10. The apparatus as recited in claim 7, further comprising:

bitlines associated with a memory;

a sense amplifier coupled to the bitlines;

wherein the output node of the interlock circuit is coupled to supply a precharge signal for the bitlines; and

wherein the second input signal is coupled to an enable input on the sense amplifier.

11. The apparatus as recited in claim 10, further comprising:

a level shifter circuit configured to receive a signal from the second voltage domain and shift a voltage level of the signal to the first voltage domain, an output of the level shifter circuit coupled to supply the first input signal to the interlock circuit.

12. A method comprising:

receiving at an interlock circuit a first input signal from a first voltage domain and a second input signal from a second voltage domain;

keeping an output node of the interlock circuit at a first voltage domain high voltage level using a keeper circuit coupled to a first power supply node associated with the first voltage domain while the first input signal is at the first voltage domain high voltage level and the second input signal is at a low voltage level; and

responsive to the second input signal transitioning from the low voltage level to a second voltage domain high voltage level while the first input signal is at the first voltage domain high voltage level, causing the output node to transition from the first voltage domain high voltage level to the low voltage level using the keeper circuit that is weaker than a pull-down circuit coupled between the output node and a ground node.

13. The method as recited in claim 12, further comprising,

supplying the second input signal to a first transistor in the keeper circuit as a first transistor gate signal thereby resulting in the keeper circuit being less strongly turned on than the pull-down circuit when the second input signal is at the second voltage domain high voltage level and the first input signal is at the first voltage domain high voltage level and the first voltage domain high voltage level is higher than the second voltage domain high voltage level.

14. The method as recited in claim 13, further comprising:

supplying the second input signal to a third transistor in the pull-down circuit as a third transistor gate signal;

supplying the first input signal to a fourth transistor in the pull-down circuit as a fourth transistor gate signal; and

coupling the output node to the ground node through the third and fourth transistors when the first input signal is at the first voltage domain high voltage level and the second input signal is at the second voltage domain high voltage level.

15. The method as recited in claim 13, further comprising using a pull-down portion of the keeper circuit to maintain the output node at the low voltage level.

16. The method as recited in claim 13, further comprising:

supplying to the first input signal to a pull-up transistor coupled between the output node and the first power supply node of the first voltage domain; and

precharging the output node to the first voltage domain high voltage level responsive to the first input signal being at the low voltage level.

17. The method as recited in claim 13, further comprising the interlock circuit supplying the low voltage level responsive to the first input signal being at the first voltage domain high voltage level and the second input signal being at the second voltage domain high voltage level.

18. The method as recited in claim 13, further comprising:

precharging bitlines of a memory based on an output of the interlock circuit; and

enabling a sense amplifier coupled to the bitlines based on the second input signal.

19. An interlock circuit comprising:

a pull-up circuit coupled to receive a first input signal to the interlock circuit from a first voltage domain and to charge an output node of the interlock circuit to a first voltage domain high voltage level responsive to the first input signal being at a low voltage level;

a first circuit including a first and second transistor serially coupled between a power supply node of the first voltage domain and an output node of the interlock circuit, the first transistor coupled to receive a second input signal to the interlock circuit from a second voltage domain as a first gate signal and the second transistor is coupled to receive a second gate signal determined according to the output node;

a pulldown circuit including a third and fourth transistor serially coupled between a ground node and the output node of the interlock circuit, the third and fourth transistors coupled to receive the first and second input signals as respective gate signals; and

wherein the interlock circuit maintains the output node at the first voltage domain high voltage level until the first input signal being at the first voltage domain high voltage level and the second input signal being at a second voltage domain high voltage level causes the interlock circuit to supply the low voltage level on the output node.

20. The interlock circuit as recited in claim 19 wherein the interlock circuit is operable when a first voltage domain high voltage level is greater than a second voltage domain high voltage level and when the first voltage domain high voltage level is less than the second voltage domain high voltage level.