Pseudo-dynamic circuit for multi-voltage timing interlocks
First Claim
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1. An apparatus comprising:
- an interlock circuit coupled to receive a first input signal from a first voltage domain and a second input signal from a second voltage domain, the interlock circuit including,a keeper circuit having a pull-up portion coupled to the second input signal and configured to maintain an output signal on an output node of the interlock circuit at a first high voltage level associated with the first voltage domain until the first input signal is at the first high voltage level and the second input signal is at a second high voltage level associated with the second voltage domain; and
a pull-down circuit coupled to receive the first input signal and the second input signal, wherein the keeper circuit is configured to be weaker than the pull-down circuit, to thereby cause the output node to transition from the first high voltage level to a low voltage level responsive to the second input signal transitioning to the second high voltage level from the low voltage level while the first input signal is at the first high voltage level.
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Abstract
An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.
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Citations
20 Claims
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1. An apparatus comprising:
an interlock circuit coupled to receive a first input signal from a first voltage domain and a second input signal from a second voltage domain, the interlock circuit including, a keeper circuit having a pull-up portion coupled to the second input signal and configured to maintain an output signal on an output node of the interlock circuit at a first high voltage level associated with the first voltage domain until the first input signal is at the first high voltage level and the second input signal is at a second high voltage level associated with the second voltage domain; and a pull-down circuit coupled to receive the first input signal and the second input signal, wherein the keeper circuit is configured to be weaker than the pull-down circuit, to thereby cause the output node to transition from the first high voltage level to a low voltage level responsive to the second input signal transitioning to the second high voltage level from the low voltage level while the first input signal is at the first high voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving at an interlock circuit a first input signal from a first voltage domain and a second input signal from a second voltage domain; keeping an output node of the interlock circuit at a first voltage domain high voltage level using a keeper circuit coupled to a first power supply node associated with the first voltage domain while the first input signal is at the first voltage domain high voltage level and the second input signal is at a low voltage level; and responsive to the second input signal transitioning from the low voltage level to a second voltage domain high voltage level while the first input signal is at the first voltage domain high voltage level, causing the output node to transition from the first voltage domain high voltage level to the low voltage level using the keeper circuit that is weaker than a pull-down circuit coupled between the output node and a ground node. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. An interlock circuit comprising:
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a pull-up circuit coupled to receive a first input signal to the interlock circuit from a first voltage domain and to charge an output node of the interlock circuit to a first voltage domain high voltage level responsive to the first input signal being at a low voltage level; a first circuit including a first and second transistor serially coupled between a power supply node of the first voltage domain and an output node of the interlock circuit, the first transistor coupled to receive a second input signal to the interlock circuit from a second voltage domain as a first gate signal and the second transistor is coupled to receive a second gate signal determined according to the output node; a pulldown circuit including a third and fourth transistor serially coupled between a ground node and the output node of the interlock circuit, the third and fourth transistors coupled to receive the first and second input signals as respective gate signals; and wherein the interlock circuit maintains the output node at the first voltage domain high voltage level until the first input signal being at the first voltage domain high voltage level and the second input signal being at a second voltage domain high voltage level causes the interlock circuit to supply the low voltage level on the output node. - View Dependent Claims (20)
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Specification