Memory device, related method, and related electronic device

• US 9,953,689 B2
• Filed: 12/28/2016
• Issued: 04/24/2018
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Kwon, Yi Jin, Ni, Hao, Yu, Hong, Yu, Chuntian
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/393,023
• Publication Number:
  US 20170110167A1
• Time in Patent Office: 482 Days
• Field of Search: 36518908, 365196, 365205
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.

Claims

1. A method of operating a memory device, the method comprising:

providing a first turn-on control signal through a first word line to a first memory cell to enable a first bit line to be electrically connected to a first source line for transmitting a first data signal through the first bit line;

turning on a first transistor to enable a first input terminal of a sense amplifier to receive the first data signal, wherein a first terminal of the first transistor is electrically connected to the first bit line, and wherein a second terminal of the first transistor is electrically connected to the first input terminal of the sense amplifier;

when providing the first turn-on signal through the first word line, providing a first turn-off control signal through a second word line to a second memory cell for disabling an electrical connection between a second bit line and a second source line; and

when turning on the first transistor, turning on a second transistor, wherein a first terminal of the second transistor is electrically connected to the second bit line, and wherein a second terminal of the second transistor is electrically connected to a second input terminal of the sense amplifier.

2. The method of claim 1, comprising:

when turning on the first transistor, turning off a third transistor, wherein a first terminal of the third transistor is electrically connected to each of the first bit line and the first transistor, wherein a second terminal of the third transistor is electrically connected to a reference bias unit, and wherein the reference bias unit is configured to provide a reference bias signal;

when turning on the second transistor, turning on a fourth transistor to enable the second input terminal of the sense amplifier to receive a first copy the reference bias signal and to enable a second copy of the reference bias signal to be transmitted to the second bit line, wherein a first terminal of the fourth transistor is electrically connected to each of the second bit line and the second transistor, wherein a second terminal of the fourth transistor is electrically connected to the reference bias unit;

using the sense amplifier to compare the first data signal with the first copy of the reference bias signal for generating a comparison result; and

providing the comparison result through an input/output unit.

3. The memory device of claim 2, wherein the first terminal of the third transistor is electrically connected to the first terminal of the first transistor regardless of whether the first transistor is turned on and regardless of whether the third transistor is turned on, and wherein the first terminal of the fourth transistor is electrically connected to the first terminal of the second transistor regardless of whether the second transistor is turned on and regardless of whether the fourth transistor is turned on.

4. The method of claim 2, comprising:

when turning on the first transistor, turning off a fifth transistor to prevent the first input terminal of the sense amplifier from receiving a first bit line bias signal, wherein a first terminal of the fifth transistor is electrically connected to each of the first bit line and the first transistor, wherein a second terminal of the fifth transistor receives the first bit line bias signal; and

when turning on the second transistor, turning off a sixth transistor to prevent the second input terminal of the sense amplifier from receiving a second bit line bias signal, wherein a first terminal of the sixth transistor is electrically connected to each of the second bit line and the second transistor, wherein a second terminal of the sixth transistor receives the second bit line bias signal.

5. The method of claim 4, wherein the first terminal of the fifth transistor is electrically connected to the first terminal of the first transistor regardless of whether the first transistor is turned on and regardless of whether the fifth transistor is turned on, and wherein the first terminal of the sixth transistor is electrically connected to the first terminal of the second transistor regardless of whether the second transistor is turned on and regardless of whether the sixth transistor is turned on.

6. The method of claim 4, comprising:

providing a second turn-off control signal through the first word line to the first memory cell for disabling an electrical connection between the first bit line and the first source line;

when providing the second turn-off control signal, providing a third turn-off control signal through the second word line to the second memory cell for disabling the electrical connection between the second bit line and the second source line; and

when providing the second turn-off control signal, turning on the fifth transistor and turning on the sixth transistor.

7. The method of claim 6, comprising:

when providing the second turn-off control signal, turning off the first transistor and turning off the second transistor.

8. The method of claim 6, comprising:

when providing the second turn-off control signal, turning off the third transistor and turning off the fourth transistor.

9. The method of claim 4, wherein a value of the first bit line bias signal is equal to a value of the second bit line bias signal.