3D semiconductor device and system

• US 9,953,870 B2
• Filed: 04/16/2017
• Issued: 04/24/2018
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Wurman, Zeev
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/488,514
• Publication Number:
  US 20170221761A1
• Time in Patent Office: 373 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4012 : for stacked arrangements of a plurality of semiconductor devices assemblies per se H01L25/00
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/01 : Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/10 : including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/66257 : Schottky transistors
• CPC Class Codes: H01L 29/6659 : with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

Claims

1. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,

wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,

wherein said first transistor is part of a control circuit controlling said second control line and said third control line,

wherein said second transistor and said third transistor are self-aligned.

2. The device according to claim 1,

wherein said second transistor is aligned to said first transistor with less than 100 nm and greater than 5 nm misalignment.

3. The device according to claim 1, further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

memory periphery circuits comprising said first transistor,

wherein said memory periphery circuits control at least said third memory cell and second memory cell.

4. The device according to claim 1,

wherein said second transistor is connected to said third transistor with an ohmic connection.

5. The device according to claim 1,

wherein said second transistor is a junction-less transistor.

6. The device according to claim 1,

wherein said second transistor comprises a schottky barrier.

7. The device according to claim 1,

wherein said second transistor comprises a second source and a second drain,

wherein said third transistor comprises a third source and a third drain,

wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.

8. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,

wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,

wherein said second transistor comprises a schottky barrier, and

wherein said second transistor and said third transistor are self-aligned.

9. The device according to claim 8,

wherein said second transistor is aligned to said first transistor with less than 100 nm and greater than 5 nm misalignment.

10. The device according to claim 8, further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

memory periphery circuits comprising said first transistor,

wherein said memory periphery circuits control at least said third memory cell and second memory cell.

11. The device according to claim 8,

wherein said second transistor is connected to said third transistor with an ohmic connection.

12. The device according to claim 8,

wherein said second transistor is a junction-less transistor.

13. The device according to claim 8,

wherein said first transistor is part of a control circuit controlling said second control line and said third control line.

14. The device according to claim 8,

wherein said second transistor comprises a second source and a second drain,

wherein said third transistor comprises a third source and a third drain,

wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.

15. A 3D integrated circuit device, comprising:

a first transistor;

a first memory cell comprising a second transistor; and

a second memory cell comprising a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said first transistor is part of a control circuit controlling said first memory cell and second memory cell,

wherein said second transistor is self-aligned to said third transistor, and

wherein said second transistor is connected to said third transistor with an ohmic connection.

16. The device according to claim 15,

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm and greater than 5 nm misalignment.

17. The device according to claim 15, further comprising:

memory periphery circuits comprising said first transistor,

wherein said memory periphery circuits control at least said first memory cell and second memory cell.

18. The device according to claim 15,

wherein said second transistor is a junction-less transistor.

19. The device according to claim 15,

wherein said second transistor comprises a schottky barrier.

20. The device according to claim 15,

wherein said second transistor comprises a second source and a second drain,

wherein said third transistor comprises a third source and a third drain,

wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.