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Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens

  • US 9,953,889 B1
  • Filed: 09/30/2016
  • Issued: 04/24/2018
  • Est. Priority Date: 12/16/2015
  • Status: Expired due to Fees
First Claim
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1. A method for making integrated circuits (ICs), comprising at least:

  • (a) performing initial processing steps to produce a test wafer that includes a first Design of Experiments (DOE) of Non-Contact Electrical Measurement (NCEM)-enabled, gate contact (GATECNT)-gate (GATE)-via-open-configured fill cells, said initial processing steps including;

    (i) patterning, on the test wafer, a first means for enabling NC detection of GATECNT-GATE via opens; and

    ,(ii) patterning, on the test wafer, a second means for enabling NC detection of GATECNT-GATE via opens;

    wherein the first and second means for enabling NC detection of GATECNT-GATE via opens are different;

    (b) determining a presence or absence of GATECNT-GATE via opens on the test wafer by;

    performing a voltage contrast examination of NCEM-enabled fill cells in the first DOE, including at least the first and second means for enabling NC detection of GATECNT-GATE via opens; and

    ,(c) using the results from step (b) to select NCEM-enabled fill cells for inclusion on a subsequent product wafer.

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