Semiconductor system and device

• US 9,953,925 B2
• Filed: 12/20/2015
• Issued: 04/24/2018
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Wurman, Zeev
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/975,830
• Publication Number:
  US 20160111369A1
• Time in Patent Office: 856 Days
• Field of Search: 257757, 257758, 257774
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Claims

1. A 3D IC device comprising:

a first semiconductor layer comprising first mono-crystallized transistors,

wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;

a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer,

wherein said at least one metal layer is in-between said first semiconductor layer and said second layer;

a global power grid to distribute power to said device overlaying said second layer; and

a local power grid to distribute power to said first mono-crystallized transistors,

wherein said global power grid is connected to said local power grid by a plurality of through second layer vias, and

wherein said vias have a radius of less than 150 nm.

2. The 3D IC device according to claim 1, further comprising:

a first alignment mark and a second alignment mark; and

wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark,

wherein at least one of said vias is aligned to said first alignment mark and said second alignment mark.

3. The 3D IC device according to claim 1,

wherein said second mono-crystallized transistors comprise horizontally oriented transistors.

4. The 3D IC device according to claim 1,

wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.

5. The 3D IC device according to claim 1, further comprising:

a heat spreader layer disposed between said second layer and said at least one metal layer.

6. The 3D IC device according to claim 1, further comprising:

a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,

wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.

7. The 3D IC device according to claim 1,

wherein at least one of said second mono-crystallized transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

or

(iv) a Finfet transistor.

8. The 3D IC device comprising:

a first semiconductor layer comprising first mono-crystallized transistors,

wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;

a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer;

wherein said at least one metal layer is disposed between said first semiconductor layer and said second layer, and

a global power grid to distribute power to said device overlaying said second layer; and

a local power grid to distribute power to said first mono-crystallized transistors,

wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,

wherein said vias have a radius of less than 150nm, and

wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.

9. The 3D IC device according to claim 8,

wherein said second mono-crystallized transistors comprise horizontally oriented transistors.

10. A 3D IC device comprising:

a first semiconductor layer comprising first mono-crystallized transistors,

wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;

a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer;

wherein said at least one metal layer is disposed between said first semiconductor layer and said second layer, and

a global power grid to distribute power to said device overlaying said second layer; and

a local power grid to distribute power to said first mono-crystallized transistors,

wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,

wherein said vias have a radius of less than 150 nm, and

wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.

11. The 3D IC device according to claim 10, further comprising:

a heat spreader layer disposed between said second layer and said at least one metal layer.

12. The 3D IC device according to claim 10, further comprising:

a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,

wherein at least one of said plurality of thermally conductive paths comprises a contact adapted to conduct heat and not conduct electricity.

13. The 3D IC device according to claim 10,

wherein at least one of said second mono-crystallized transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

or

(iv) a Finfet transistor.

14. A 3D IC device comprising:

a first semiconductor layer comprising first mono-crystallized transistors,

wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper; and

a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer,

wherein said at least one metal layer is in-between said first semiconductor layer and said second layer, and

a global power grid to distribute power to said device overlaying said second layer; and

a local power grid to distribute power to said first mono-crystallized transistors,

wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,

wherein said vias have a radius of less than 150 nm, and

wherein at least one of said second mono-crystallized transistors is one of;

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

or

(iv) a Finfet transistor.

15. The 3D IC device according to claim 14, further comprising:

a heat spreader layer between said second layer and said at least one metal layer.

16. The 3D IC device according to claim 14, further comprising:

a first alignment mark and a second alignment mark; and

wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark,

wherein at least one of said vias is aligned to said first alignment mark and said second alignment mark.

17. The 3D IC device according to claim 14,

wherein said second mono-crystallized transistors comprise horizontally oriented transistors.

18. The 3D IC device according to claim 14,

wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.

19. The 3D IC device according to claim 14, further comprising:

a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,

wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.

20. The 3D IC device according to claim 14, further comprising:

a back-gate structure for at least one of said second mono-crystallized transistors.