Package substrate and package structure using the same

• US 9,953,956 B2
• Filed: 03/18/2016
• Issued: 04/24/2018
• Est. Priority Date: 03/18/2015
• Status: Active Grant

• Current Assignee: Nichia Corporation
• Original Assignee: Genesis Photonics Inc.
• Inventors: Lee, Hao-Chung, Lin, Yu-Feng, Zhan, Xun-Xain
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US15/073,707
• Publication Number:
  US 20160284666A1
• Time in Patent Office: 767 Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/18161 of a flip chip
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/48 : characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/502 : Wavelength conversion materials
• CPC Class Codes: H01L 33/508 : having a non-uniform spatial arrangement or non-uniform concentration, e.g. patterned wavelength conversion layer, wavelength conversion layer with a concentration gradient of the wavelength conversion material
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A package substrate is provided. The package substrate includes a base layer having a first surface and a second surface opposite to the first surface, a plurality of through holes penetrating the base layer, a first metal layer disposed on the first surface, and a second metal layer disposed on the second surface. The first metal layer includes a closed-loop trench. A part of the second metal layer is electrically connected to the first metal layer via the through holes. The through holes are positioned at an inner part the closed-loop trench.

Claims

1. A package substrate, comprising:

a base layer having a first surface and a second surface opposite to the first surface;

a plurality of through holes penetrating through the base layer;

a first metal layer disposed on the first surface and comprising an encircling portion and a plurality of upper pads arranged separately, wherein the encircling portion surrounds the upper pads to form a closed-loop trench between the encircling portion and the upper pads, and at least one gap between the upper pads intercommunicates with the closed-loop trench; and

a second metal layer disposed on the second surface comprising a plurality of bottom pads arranged separately, wherein the bottom pads are electrically connected to the upper pads via the through holes respectively;

wherein the through holes are positioned under the upper pads and the encircling portion of the first metal layer is electrically floating.

2. The package substrate according to claim 1, wherein the second metal layer further comprises:

a heat dissipation region comprising a plurality of heat dissipation pads separated by a plurality of trenches.

3. The package substrate according to claim 1, wherein a width of the closed-loop trench is from 80 to 300 μ

m.

4. The package substrate according to claim 1, wherein a depth of the closed-loop trench is from 40 to 80 μ

m.

5. The package substrate according to claim 1, wherein the base layer comprises a ceramic material.

6. The package substrate according to claim 1, further comprising a plating layer formed on the first metal layer and the second metal layer, wherein the plating layer is formed of gold or silver.

7. The package substrate according to claim 2, wherein the heat dissipation pads are electrically floating.

8. The package substrate according to claim 2, wherein the bottom pads of the second metal layer are divided into an anode region and a cathode region separated from and surrounding the heat dissipation region.

9. A package structure, comprising:

a package substrate, comprising;

a base layer having a first surface and a second surface opposite to the first surface;

a plurality of through holes penetrating through the base layer;

a first metal layer disposed on the first surface and comprising an encircling portion and a plurality of upper pads arranged separately, wherein the encircling portion surrounds the upper pads to form a closed-loop trench between the encircling portion and the upper pads, and at least one gap between the upper pads intercommunicates with the closed-loop trench; and

a second metal layer disposed on the second surface comprising a plurality of bottom pads arranged separately, wherein the bottom pads are electrically connected to the upper pads via the through holes respectively, and the encircling portion of the first metal layer is electrically floating; and

at least one chip disposed on the upper pads and electrically connected thereto; and

an encapsulant layer disposed on the package substrate and covering the chip and at least a portion of the upper pads, wherein the encapsulant layer do not extend beyond an outer wall of the closed-loop trench.

10. The package structure according to claim 9, wherein the second metal layer further comprising:

a heat dissipation region corresponding to the chip, comprising a plurality of heat dissipation pads separated by a plurality of trenches.

11. The package structure according to claim 10, wherein the bottom pads of the second metal layer are divided into an anode region and a cathode region separated from and surrounding the heat dissipation region.

12. The package structure according to claim 9, wherein the chip comprises a flip chip.

13. The package structure according to claim 9, wherein when a quantity of the chip is plural, a distances between the chips is 50 μ

m.

14. The package structure according to claim 9, wherein a distance between the closed-loop trench and the chip is from 500 to 2000 μ

m.

15. The package structure according to claim 9, wherein the encapsulant layer comprises a resin material mixed with phosphor powder.

16. The package structure according to claim 9, wherein the package substrate further comprises:

a plating layer formed on the first metal layer and the second metal layer;

wherein the plating layer is formed of gold or silver.

17. The package structure according to claim 10, wherein the heat dissipation pads are electrically floating.

18. A package structure, comprising:

a package substrate, comprising;

a base layer having a first surface and a second surface opposite to the first surface;

a plurality of through holes penetrating the base layer;

a first metal layer disposed on the first surface and comprising a closed-loop trench; and

a second metal layer disposed on the second surface, wherein a part of the second metal layer is electrically connected to the first metal layer via the through holes; and

a chipset and an encapsulant layer disposed on the first metal layer and positioned at an inner part of the closed-loop trench,

wherein the second metal layer further comprising a heat dissipation region corresponding to the chipset, and the heat dissipation region is formed of a plurality of trenches arranged in an array of pads,

wherein the second metal layer further comprises an anode region and a cathode region separated from the heat dissipation region, wherein each of a distance between the anode region and the cathode region, a distance between the anode region and the heat dissipation region, and a distance between the cathode region and the heat dissipation region is at least 400 μ

m.