Semiconductor system, device and structure

• US 9,953,972 B2
• Filed: 03/27/2017
• Issued: 04/24/2018
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US15/470,866
• Publication Number:
  US 20170200715A1
• Time in Patent Office: 393 Days
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

Claims

1. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of through silicon vias (TSVs);

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of second transistors overlaying said at least one metal layer;

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,

wherein at least one of said plurality of second transistors comprises a polysilicon channel,

wherein at least one of said plurality of second transistors is junction-less transistor,

wherein each of said plurality of second transistors comprises a gate, and

wherein formation of said gate comprises Atomic Layer Deposition (ALD).

2. The 3D semiconductor device according to claim 1, further comprising:

wherein at least one of said third transistors is a double gate transistor, and

wherein each gate of said double gate transistor is independently controlled.

3. The 3D semiconductor device according to claim 1, further comprising:

a NAND type flash memory comprising said first memory array.

4. The 3D semiconductor device according to claim 1, further comprising:

a top metal layer overlaying said plurality of third transistors; and

a plurality of fourth transistors overlaying said top metal,

wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.

5. The 3D semiconductor device according to claim 1,

wherein each of said plurality of second transistors comprises a gate dielectric, and

wherein said gate dielectric comprises a low temperature microwave plasma oxide.

6. The 3D semiconductor device according to claim 1,

wherein at least one of said first transistors is of the dopant segregated schottky barrier type.

7. The 3D semiconductor device according to claim 1,

wherein at least one of said plurality of second transistors directly overlays at least one of said TSVs.

8. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of through silicon vias (TSVs);

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of second transistors overlaying said at least one metal layer;

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,

wherein at least one of said plurality of second transistors comprises a polysilicon channel, and

wherein at least one of said plurality of second transistors is junction-less transistor.

9. The 3D semiconductor device according to claim 8,

wherein at least one of said second transistors is a double gate transistor, and

wherein each gate of said double gate transistor is independently controlled.

10. The 3D semiconductor device according to claim 8,

wherein at least one of said first transistors is of the dopant segregated schottky barrier type.

11. The 3D semiconductor device according to claim 8, further comprising:

a NAND type flash memory comprising said first memory array.

12. The 3D semiconductor device according to claim 8, further comprising:

a top metal layer overlaying said plurality of third transistors; and

a plurality of fourth transistors overlaying said top metal,

wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.

13. The 3D semiconductor device according to claim 8,

wherein said plurality of fourth transistors are part of a memory periphery circuit.

14. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of through silicon vias (TSVs);

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of second transistors overlaying said at least one metal layer;

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors.

15. The 3D semiconductor device according to claim 14,

wherein at least one of said plurality of second transistors comprises a polysilicon channel.

16. The 3D semiconductor device according to claim 14,

wherein at least one of said second transistors is a double gate transistor, and

wherein each gate of said double gate transistor is independently controlled.

17. The 3D semiconductor device according to claim 14,

wherein at least one of said first transistors is of the dopant segregated schottky barrier type.

18. The 3D semiconductor device according to claim 14,

wherein at least one of said plurality of second transistors is a junction-less transistor.

19. The 3D semiconductor device according to claim 14, further comprising:

a NAND type flash memory comprising said plurality of second transistors.

20. The 3D semiconductor device according to claim 14, further comprising:

a top metal layer overlaying said plurality of third transistors; and

a plurality of fourth transistors overlaying said top metal,

wherein a subset of said plurality of first transistors are part of peripheral circuit controlling said first memory array.