Method and apparatus for improving read margin for an SRAM bit-cell

• US 9,953,986 B2
• Filed: 12/20/2013
• Issued: 04/24/2018
• Est. Priority Date: 12/20/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Yih
• Primary Examiner(s): Bradley, Stephen
• Assistant Examiner(s): REDDINGTON, PATRICIA D
• Application Number:
  US14/137,879
• Publication Number:
  US 20150179653A1
• Time in Patent Office: 1,586 Days
• Field of Search: 257369
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension.

Claims

1. An SRAM cell comprising:

a first n-type transistor with a gate terminal coupled to word-line (WL), a source/drain terminal coupled to a first bit-line (BL) and a drain/source terminal coupled to a first node; and

,

a second n-type transistor with a source terminal coupled to a reference node, a drain terminal coupled to the first node, and a gate terminal coupled to a second node, wherein the gate terminal includes an integrated capacitor to increase coupling capacitance between the first and second nodes, the integrated capacitor comprising a bottom electrode formed with a same conductive layer used to form the gate terminal of the second n-type transistor, the integrated capacitor having a length that does not extend beyond a single gate length, wherein a spacing on either side of the gate terminals of the first and second n-type transistors is asymmetric such that a spacing between the gate terminal of the first n-type transistor and a diffusion contact region associated with the first node is smaller than a spacing between the gate terminal of the first n-type transistor and a diffusion contact region associated with the first BL.

2. The SRAM cell of claim 1 further comprises:

a first p-type transistor with a source terminal coupled to a power supply node and a drain terminal coupled to the first node, wherein the gate terminals of the first p-type transistor and the second n-type transistor are coupled to a second node; and

a third n-type transistor with a source terminal coupled to the reference node, a drain terminal coupled to the second node, and a gate terminal coupled to the first node, wherein the gate terminal of the third n-type transistor includes a second integrated capacitor to increase coupling capacitance between the first and the second nodes.

3. The SRAM cell of claim 2 further comprises:

a second p-type transistor with a source terminal coupled to the power supply node and a drain terminal coupled to the second node, wherein the gate terminals of the third n-type transistor and the second p-type transistor are coupled to the first node; and

a fourth n-type transistor with a gate terminal coupled to the WL, a source/drain terminal coupled to a second BL, and a drain/source terminal coupled to the second node.

4. The SRAM cell of claim 1, wherein the spacing between the gate terminal of the first n-type transistor and the diffusion contact region associated with the first node is formed of High-K dielectric material.

5. The SRAM cell of claim 1, wherein the spacing between the gate terminal of the first n-type transistor and the diffusion contact region associated with the first BL is formed of a Low-K dielectric material.

6. A system comprising:

a memory unit;

a processor coupled to the memory unit, the processor having an SRAM cell which includes;

a first n-type transistor with a gate terminal coupled to word-line (WL), a source/drain terminal coupled to a first bit-line (BL) and a drain/source terminal coupled to a first node; and

,

a second n-type transistor with a source terminal coupled to a reference node, a drain terminal coupled to the first node, and a gate terminal coupled to a second node, wherein the gate terminal includes an integrated capacitor to increase coupling capacitance between the first and second nodes, the integrated capacitor comprising a bottom electrode formed with a same conductive layer used to form the gate terminal of the second n-type transistor, the integrated capacitor having a length that does not extend beyond a single gate length, wherein a spacing on either side of the gate terminals of the first and second n-type transistors is asymmetric such that a spacing between the gate terminal of the first n-type transistor and a diffusion contact region associated with the first node is smaller than a spacing between the gate terminal of the first n-type transistor and a diffusion contact region associated with the first BL; and

a wireless interface for coupling the processor to another device.

7. The system of claim 6, wherein the layer of conductive material serves as a bottom electrode of the integrated capacitor.