Vertical power MOSFET device

• US 9,954,055 B2
• Filed: 08/29/2016
• Issued: 04/24/2018
• Est. Priority Date: 03/08/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kobayashi, Kenya, Arai, Masatoshi
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ahmed, Shahed
• Application Number:
  US15/250,555
• Publication Number:
  US 20170263699A1
• Time in Patent Office: 603 Days
• Field of Search: 257330, 257335, 257520, 438133, 438270, 438361, 438429
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a layer having first and second surfaces and a first type first region, a second type second region in the layer between the first region and first surface, a first type third region in the layer between the second region and first surface, first and second gate electrodes, wherein the second region is between the first and second gate electrodes, a first field plate electrode between the second surface and first gate electrode, a second field plate electrode between the second surface and second gate electrode, a first film, at least a portion between the first field plate electrode and first region, a second film at least a portion between the second field plate electrode and first region, and a second type fourth region in the first region between the first and second films. A portion of the first region is between second and fourth regions.

Claims

1. A semiconductor device, comprising:

a semiconductor layer having a first surface and a second surface;

a first semiconductor region of a first conductivity type in the semiconductor layer;

a second semiconductor region of a second conductivity type in the semiconductor layer between the first semiconductor region and the first surface;

a third semiconductor region of the first conductivity type in the semiconductor layer between the second semiconductor region and the first surface;

a first gate electrode on the semiconductor layer;

a second gate electrode on the semiconductor layer, wherein the second semiconductor region is between the first gate electrode and the second gate electrode;

a first field plate electrode between the second surface and the first gate electrode;

a second field plate electrode between the second surface and the second gate electrode;

a first insulating film having at least a portion between the first field plate electrode and the first semiconductor region;

a second insulating film having at least a portion between the second field plate electrode and the first semiconductor region; and

a plurality of fourth semiconductor regions of the second conductivity type in the first semiconductor region between and separated from the first insulating film and the second insulating film, wherein the plurality of fourth semiconductor regions are separated from each other and the second semiconductor region by the first semiconductor region, wherein

a width of each fourth semiconductor region in a direction perpendicular to the first surface is less than a distance between adjacent fourth semiconductor regions.

2. The semiconductor device according to claim 1, wherein:

the first semiconductor region is between the plurality of fourth semiconductor regions and the first insulating film, and

the first semiconductor region is between the plurality of fourth semiconductor regions and the second insulating film.

3. The semiconductor device according to claim 1, wherein the width of each fourth semiconductor region in the direction perpendicular to the first surface is smaller than the distance between the fourth semiconductor region and the second semiconductor region.

4. The semiconductor device according to claim 1, further comprising:

a fifth semiconductor region of the second conductivity type in the first semiconductor region between the fourth semiconductor region and the second surface, wherein a portion of the first semiconductor region is between the fourth semiconductor region and the fifth semiconductor region; and

a sixth semiconductor region of the second conductivity type in the first semiconductor region between the fifth semiconductor region and the second surface, wherein at least a portion of the first semiconductor region is between the fifth semiconductor region and the sixth semiconductor region.

5. The semiconductor device according to claim 4, wherein the widths of the first, second, and third semiconductor regions in the direction perpendicular to the first surface is greater than the thicknesses thereof, respectively, in the direction perpendicular to the first surface.

6. The semiconductor device according to claim 1, wherein:

the first insulating film is between the first field plate electrode and the first gate electrode, and

the second insulating film is between the second field plate electrode and the second gate electrode.

7. The semiconductor device according to claim 1, wherein the first gate electrode and the first field plate electrode contact each other.

8. The semiconductor device according to claim 7, wherein the second gate electrode and the second field plate electrode contact each other.

9. The semiconductor device according to claim 1, wherein the first and second field plate electrodes and the first and second gate electrodes comprise polysilicon.

10. A semiconductor device, comprising:

a semiconductor layer comprising a first surface and a second surface opposed to the first surface, the semiconductor layer comprising;

a first region of a first conductivity type extending into the semiconductor layer from the first surface;

a second region of a second conductivity type between the first region and the first surface;

a third region of the first conductivity type between the second region and the first surface; and

a plurality of fourth regions of the second conductivity type between the second region and the second surface, wherein

the fourth regions are separated from each other and the second semiconductor region by portions of the first region, and

a width of each fourth region in a direction perpendicular to the first surface is less than a distance between adjacent fourth regions;

a first trench extending inwardly of the first surface and terminating within the first region; and

a second trench extending inwardly of the first surface and terminating within the first region,

wherein the plurality of fourth semiconductor regions is between and separated from the first and second trenches in a portion of the first region that extends from the first trench to the second trench and contacts the second region.

11. The semiconductor device according to claim 10, further comprising:

a first field plate electrode in the first trench and extending therein in a direction between the first and second surfaces; and

a first insulating layer extending between the first field plate electrode and the adjacent inner surfaces of the first trench.

12. The semiconductor device according to claim 11, further comprising a gate electrode in the first trench and overlying the first field plate electrode.

13. The semiconductor device according to claim 12, wherein the semiconductor layer further comprises a fifth region of the second conductivity type between the first and the second trenches, and between the fourth region and the second surface.

14. The semiconductor device according to claim 12, wherein the semiconductor layer further comprises a sixth region of the second conductivity type between the second region and the first surface, wherein the third region is located on the sides of the sixth region in a direction parallel to the first surface, and wherein a first electrode overlies the first surface and contacts the third region and the sixth region.

15. The semiconductor device according to claim 14, further comprising a second insulating layer between the first gate electrode and the second region, the third region, and the first electrode.

16. The semiconductor device according to claim 15, further comprising a second electrode overlying the second surface and contacting the first region.

17. The semiconductor device according to claim 14, wherein a concentration of second conductivity type impurity is greater in the sixth region than a concentration of second conductivity type impurity in the second region.

18. A semiconductor device, comprising:

a first electrode;

a first semiconductor layer of a first conductivity type on the first electrode;

a second semiconductor layer of a second conductivity type on the first semiconductor layer;

a third semiconductor layer of the first conductivity type on the second semiconductor layer;

a plurality of trenches extending through the third semiconductor layer and the second semiconductor layer and terminating in the first semiconductor layer, at least two adjacent trenches in the plurality of trenches including a field plate electrode and a gate electrode located therein, wherein the field plate electrode is between the gate electrode and the first electrode; and

a plurality of fourth semiconductor layers of the second conductivity type between the at least two adjacent trenches, and between the first electrode and the second semiconductor layer, wherein

the fourth semiconductor layers are in the first semiconductor layer and separated from each other, the plurality of trenches, and the first electrode by a portion of the first semiconductor layer, and

a thickness of each fourth semiconductor layer is less than a distance between adjacent fourth semiconductor layers.

19. The semiconductor device according to claim 18, wherein the thickness of the fourth semiconductor layer of the plurality of fourth semiconductor layers that is closest to the second semiconductor layer is less than the distance between that fourth semiconductor layer and the second semiconductor layer.

20. The semiconductor device according to claim 19, wherein the thicknesses of adjacent fourth semiconductor layers in the plurality of fourth semiconductors are different.