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Method of forming a transistor, method of patterning a substrate, and transistor

  • US 9,954,068 B2
  • Filed: 09/25/2015
  • Issued: 04/24/2018
  • Est. Priority Date: 09/30/2014
  • Status: Active Grant
First Claim
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1. A method of forming a transistor including a gate electrode, the method comprising:

  • forming a sacrificial layer over a semiconductor substrate;

    forming a patterning layer over the sacrificial layer;

    patterning the patterning layer to form patterned structures;

    forming spacers adjacent to sidewalls of the patterned structures;

    removing the patterned structures;

    etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, wherein semiconductor mesas are defined by adjacent ones of the trenches;

    filling a conductive material in the trenches in the semiconductor substrate to form gate electrodes;

    forming a body region of a second conductivity type in the semiconductor mesas, a source region of a first conductivity type in the body region and a drift zone of the first conductivity type below the body region such that the conductive material extends above an upper surface of the source region;

    selectively removing the etching mask to define a first opening over the semiconductor substrate to form a gate contact to a gate electrode, the first opening having a greater width than a width of the trench; and

    selectively removing the etching mask to define a second opening over the semiconductor substrate to form a mesa contact to a semiconductor mesa such that at least one of two adjacent semiconductor mesas is not in contact with the mesa contact, the second opening having a greater width than a distance between adjacent trenches, a width of a bottom portion of mesa contact contacting the semiconductor mesa being less than a width of the semiconductor mesa.

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