Thyristor random access memory device and method
First Claim
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1. A method comprising:
- forming two vertically coupled P-N junctions on a first substrate;
forming a conductor region over the two vertically coupled P-N junctions;
flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate;
forming a third vertically coupled P-N junction on a back side of a portion of the first substrate;
forming a control line between two of the vertically coupled P-N junctions;
forming a buried transmission line from a portion of the conductor region; and
forming a second transmission line on top of the third vertically coupled P-N junction.
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Abstract
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
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Citations
18 Claims
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1. A method comprising:
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forming two vertically coupled P-N junctions on a first substrate; forming a conductor region over the two vertically coupled P-N junctions; flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate; forming a third vertically coupled P-N junction on a back side of a portion of the first substrate; forming a control line between two of the vertically coupled P-N junctions; forming a buried transmission line from a portion of the conductor region; and forming a second transmission line on top of the third vertically coupled P-N junction. - View Dependent Claims (2, 3, 4, 5)
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6. A method comprising:
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forming a vertical stack of alternating conductivity type semiconductor material, including; forming two vertically coupled P-N junctions on a first substrate; forming a conductor region over the two vertically coupled P-N junctions; flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate; forming a third vertically coupled P-N junction on a back side of a portion of the first substrate; forming trenches in the vertical stack to form an array of vertical pillars of alternating conductivity type semiconductor material; and forming at least one control line in a trench between two adjacent pillars separated from a channel region by a dielectric material. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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forming a P-N-P layer structure to form a first substrate; forming a conductor region over the first substrate; flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate; forming an N layer on a back side of a portion of the first substrate; forming a trench at least partially through the N layer and the P-N-P layer; and forming a control line within the trench. - View Dependent Claims (16, 17, 18)
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Specification