3D integrated circuit device

• US 9,954,080 B2
• Filed: 06/14/2017
• Issued: 04/24/2018
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/622,124
• Publication Number:
  US 20170287844A1
• Time in Patent Office: 314 Days
• Field of Search: 257369, 257499
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80012 Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
• CPC Class Codes: H01L 2224/80013 Plasma cleaning
• CPC Class Codes: H01L 2224/8013 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/80132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 : in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 : oriented parallel to a substrate
• CPC Class Codes: H01L 29/1066 : Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.

Claims

1. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said first transistor controls the supply of a ground or a power signal to said third transistor, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

2. The device according to claim 1,

wherein said second transistor and said third transistor are junction-less transistors.

3. The device according to claim 1, further comprising:

a second transistor gate dielectric; and

a third transistor gate dielectric,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer.

4. The device according to claim 1,

wherein said second transistor and said third transistor each have a first gate and a second gate.

5. The device according to claim 1,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate, and

wherein said first gate is not connected to said second gate.

6. The device according to claim 1,

wherein said third transistor is controlled by a third control line,

wherein said second transistor is controlled by a second control line, and

wherein said first transistor is part of a control circuit controlling said second control line and third control line.

7. The device according to claim 1,

wherein said second transistor is self-aligned to said third transistor.

8. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor, said second transistor has a second transistor gate dielectric; and

a third transistor, said third transistor has a third transistor gate dielectric,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said second transistor and said third transistor are junction-less transistors,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

9. The device according to claim 8, further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

a memory periphery circuit comprising said first transistor,

wherein said memory periphery circuits control said third memory cell and second memory cell.

10. The device according to claim 8,

wherein said second transistor is connected to said third transistor with an ohmic connection.

11. The device according to claim 8,

wherein said second transistor and said third transistor each have a first gate and a second gate.

12. The device according to claim 8,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate, and

wherein said first gate is not connected to said second gate.

13. The device according to claim 8,

wherein said third transistor is controlled by a third control line,

wherein said second transistor is controlled by a second control line, and

wherein said first transistor is part of a control circuit controlling said second control line and third control line.

14. The device according to claim 8,

wherein said second transistor is self-aligned to said third transistor.

15. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said second transistor and said third transistor each have a first gate and a second gate,

wherein said second transistor first gate is connected to said third transistor first gate,

wherein said first gate is not connected to said second gate, and

wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.

16. The device according to claim 15, further comprising:

a third memory cell comprising said third transistor;

a second memory cell comprising said second transistor; and

a memory periphery circuit comprising said first transistor,

wherein said memory periphery circuit controls said third memory cell and second memory cell.

17. The device according to claim 15,

wherein said second transistor is connected to said third transistor with an ohmic connection.

18. The device according to claim 15,

wherein said second transistor and said third transistor are junction-less transistors.

19. The device according to claim 15, further comprising:

a second transistor gate dielectric; and

a third transistor gate dielectric,

wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer.

20. The device according to claim 15,

wherein said second transistor is self-aligned to said third transistor.