Semiconductor structures having increased channel strain using fin release in gate regions

• US 9,954,083 B2
• Filed: 08/20/2015
• Issued: 04/24/2018
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Lu, Darsen D., Reznicek, Alexander, Rim, Kern
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US14/830,789
• Publication Number:
  US 20170053994A1
• Time in Patent Office: 978 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Claims

1. A strained FinFET structure, comprising:

a lower fin material formed on a substrate, the lower fin material disposed at opposing ends of a channel region;

an upper fin material formed on the lower fin material, the upper fin material comprising a strained semiconductor material, and wherein the lower fin material comprises a material that is etch selective with respect to the upper fin material;

wherein the channel region below the upper portion comprises a removed section of the lower fin material such that the upper fin material in the channel region is released from the substrate, thereby resulting in strain introduced throughout an entire height of the upper fin material in the channel region; and

a carbon doped silicon (Si;

C) diffusion barrier disposed between the lower fin material and the upper fin material;

wherein the lower fin material comprises n-doped silicon having a dopant concentration of about 1E21 atoms/cm²;

the upper fin material comprises a compressively stressed silicon germanium (SiGe) layer having a germanium concentration of about 25% Ge atomic.

2. The structure of claim 1, wherein the removed section of the lower fin material is filled with one of an insulating material and a semiconductor material.