Semiconductor device and method of manufacturing same

• US 9,954,095 B2
• Filed: 01/08/2017
• Issued: 04/24/2018
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Moriya, Taro, Kudou, Hiroyoshi, Uchiya, Satoshi
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/401,095
• Publication Number:
  US 20170263753A1
• Time in Patent Office: 471 Days
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first surface and a second surface, which is a surface on a side of the semiconductor substrate opposite to the first surface;

a drain region in the semiconductor substrate proximal to the second surface and having a first conductivity type;

a drift region in the semiconductor substrate between the first surface and the drain region, and having the first conductivity type;

a base region in the semiconductor substrate between the first surface and the drift region, and having a second conductivity type;

a source region in the semiconductor substrate at the first surface, and having the first conductivity type, the base region being sandwiched between the source region and the drift region;

a gate electrode opposite to the base region sandwiched between the drift region and the source region, the gate electrode being insulated from the base region;

a wiring provided over the first surface and electrically coupled to the source region; and

a first conductive film provided over the first surface and electrically coupled to the drain region,

wherein the first conductive film is, over the first surface, opposite to the wiring while being insulated therefrom.

2. The semiconductor device according to claim 1, further comprising a first interlayer insulating film provided between the wiring and the first surface,

wherein the first conductive film is provided in the first interlayer insulating film.

3. The semiconductor device according to claim 1, further comprising a second interlayer insulating film formed over the wiring,

wherein the first conductive film is present over the second interlayer insulating film.

9. The semiconductor device according to claim 1, further comprising a contact plug having:

a lower contact plug located between the wiring and the source region and electrically coupled to the source region; and

an upper contact plug located over the lower contact plug and electrically coupled to the wiring and the lower contact plug,

wherein the first conductive film and the lower contact plug are formed of the same material.

10. The semiconductor device according to claim 9, further comprising a second conductive film placed over the first surface and coupled to the source region,

wherein the second conductive film is opposite to the first conductive film while being insulated therefrom, and

wherein the first conductive film and the second conductive film are formed of the same material and are formed in a same layer.

11. The semiconductor device according to claim 1, further comprising:

a column region provided in the semiconductor substrate, extending in the drift region from the base region toward the second surface, and having the second conductivity type.

12. The semiconductor device according to claim 1,

wherein the wiring is conductively connected to the source region,

the first conductive film is conductively connected to the drain region, and

in an off-state of the semiconductor device, the first conductive film is not conductively connected to the wiring.

13. The semiconductor device according to claim 1, further comprising:

a second wiring over the first surface and conductively connected to the source region via a contact plug that extends between the drift region and the second wiring,

wherein the first conductive film is connected to the second wiring such that the first conductive film is conductively connected to the drain region via the second wiring.

14. The semiconductor device according to claim 1, wherein

a first capacitance is formed between the base region and the drift region,

a second capacitance is formed between the wiring and the first conductive film, and

the first capacitance and the second capacitance act as capacitances in parallel between the source and drain regions.

15. The semiconductor device according to claim 1, further comprising:

a second conductive film electrically coupled to the source region,

wherein a portion of the first conductive film faces a portion of the second conductive film, and

the first and second conductive films are insulated from each other.

16. The semiconductor device according to claim 15, wherein an insulating film separating the facing portions of the first and second conductive films has a dielectric constant that is higher than that of an insulating film between the wiring and the first conductive film or an insulating film between the first conductive film and the source region.

17. The semiconductor device according to claim 15, wherein the first and second conductive films are formed from a same layer and are co-planar.

18. The semiconductor device according to claim 15, wherein a first plug portion couples the source region to the second conductive film, and a second plug portion couples the second conductive film to the wiring, the second conductive film being between the first and second plug portions.

19. The semiconductor device according to claim 15, wherein the first and second conductive films are formed of a material comprising aluminum.

4. A semiconductor device, comprising:

a semiconductor substrate having a first surface and a second surface, which is a surface on a side of the semiconductor substrate opposite to the first surface;

a drain region in the semiconductor substrate proximal to the second surface, and having a first conductivity type;

a drift region in the semiconductor substrate between the first surface and the drain region, and having the first conductivity type;

a base region in the semiconductor substrate between the first surface and the drift region, and having a second conductivity type;

a source region in the semiconductor substrate at the first surface, and having the first conductivity type, the base region being sandwiched between the source region and the drift region;

a gate electrode opposite to the base region sandwiched between the drift region and the source region, the gate electrode being insulated from the base region;

a wiring provided over the first surface and electrically coupled to the source region;

a first conductive film provided over the first surface and electrically coupled to the drain region;

a first interlayer insulating film provided between the wiring and the first surface; and

a second conductive film placed over the first surface and coupled to the source region,

wherein the first conductive film is, over the first surface, opposite to the wiring while being insulated therefrom,

wherein the first conductive film is provided in the first interlayer insulating film, and

wherein the second conductive film is opposite to the first conductive film while being insulated therefrom.

5. The semiconductor device according to claim 4, further comprising a dielectric film provided between the first conductive film and the second conductive film,

wherein the dielectric film has a dielectric constant higher than that of the first interlayer insulating film.

6. The semiconductor device according to claim 4,

wherein the first conductive film and the second conductive film are formed of the same material and are formed in a same layer.

7. The semiconductor device according to claim 6, further comprising a contact plug having:

a lower contact plug located between the second conductive film and the source region and electrically coupling the second conductive film to the source region; and

an upper contact plug located over the second conductive film and coupled to the wiring and the second conductive film,

wherein the second conductive film is placed at a height position between a height position of the lower contact plug and a height position of the upper contact plug.

8. The semiconductor device according to claim 6,

wherein either aluminum or an aluminum alloy is used as a material of each of the first conductive film and the second conductive film.