Single μC-buckboost converter with multiple regulated supply outputs

• US 9,954,436 B2
• Filed: 09/29/2011
• Issued: 04/24/2018
• Est. Priority Date: 09/29/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Khlat, Nadim
• Primary Examiner(s): Mourad, Rasem
• Application Number:
  US13/876,518
• Publication Number:
  US 20130181521A1
• Time in Patent Office: 2,399 Days
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

The detailed description described embodiments of highly efficient power management systems configurable to simultaneously generate various output voltage levels for different components, sub-assemblies, and devices of electronic devices, sub-systems, and systems. In particular, the described embodiments include power management systems that substantially reduce or eliminate the need for inductors, large numbers of capacitors, and complex switching techniques to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. Some described embodiments include a charge pump that uses only two flying capacitors to simultaneously generate multiple supply outputs, where each of the multiple supply outputs may provide either the same or a different output voltage level. The described embodiments also include efficient power management systems that flexibly provide highly accurate voltage levels that are substantially insensitive to the voltage level provided by a system power source, such as a battery.

Claims

1. An apparatus comprising:

a first flying capacitor;

a second flying capacitor;

a switch matrix having an input, a first output, and a second output to which the first flying capacitor and the second flying capacitor are selectively coupled; and

a controller configured to, in response to a given value X of a ratio between a supply voltage V_S at the input and a first desired output voltage at the first output, control the switch matrix to couple the first flying capacitor and the second flying capacitor to the input in a charging arrangement corresponding to the given value X during a charge phase, and during a first discharge phase couple the first flying capacitor and the second flying capacitor to the first output in a first discharging arrangement corresponding to the given value X to generate the first desired output voltage, and during a second discharge phase couple the first flying capacitor and the second flying capacitor to the second output in a second discharging arrangement corresponding to the given value X to generate a second desired output voltage, wherein the switch matrix and controller are configured to;

include a first boost/buck mode that generates a voltage equal to (7/4)·

V_S for the first desired output voltage in which the second desired output voltage is less than V_S; and

include a first buck/boost mode that at least generates a voltage that is equal to (7/4)·

V_S for the second desired output voltage in which the first desired output voltage is less than V_S.

2. The apparatus of claim 1 wherein the first desired output voltage is equal to X·

V_S and the second desired output voltage is equal to (1−

X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4 in a buck/buck mode.

3. The apparatus of claim 1 wherein the first desired output voltage is equal to (1−

X)·

V_S and the second desired output voltage is equal to X·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4 in a buck/buck mode.

4. The apparatus of claim 1 wherein the first desired output voltage is equal to X·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4, and the second desired output voltage is equal to (1+X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, and 2/3 in a second buck/boost mode.

5. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the charging arrangement.

6. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the charging arrangement.

7. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the first discharging arrangement.

8. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the first discharging arrangement.

9. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the second discharging arrangement.

10. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the second discharging arrangement.

11. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the charging arrangement, the first discharging arrangement, and the second discharging arrangement.

12. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in both the charging arrangement and the first discharging arrangement, and the first flying capacitor and the second flying capacitor are coupled in parallel in the second discharging arrangement.

13. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the charging arrangement, the first flying capacitor and the second flying capacitor are coupled in parallel in the first discharging arrangement, and the first flying capacitor and the second flying capacitor are coupled in series in the second discharging arrangement.

14. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in series in the charging arrangement, and the first flying capacitor and the second flying capacitor are coupled in both the first discharging arrangement and the second discharging arrangement.

15. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the charging arrangement, and the first flying capacitor and the second flying capacitor are coupled in both the first discharging arrangement and the second discharging arrangement.

16. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the charging arrangement, the first flying capacitor and the second flying capacitor are coupled in series in the first discharging arrangement, and the first flying capacitor and the second flying capacitor are coupled in parallel in the second discharging arrangement.

17. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in both the charging arrangement and the first discharging arrangement, and the first flying capacitor and the second flying capacitor are coupled in series in the second discharging arrangement.

18. The apparatus of claim 1 wherein the first flying capacitor and the second flying capacitor are coupled in parallel in the charging arrangement, the first discharging arrangement, and the second discharging arrangement.

19. The apparatus of claim 1 further including a first holding capacitor coupled between the first output and a fixed voltage node.

20. The apparatus of claim 19 further including a second holding capacitor coupled between the second output and the fixed voltage node.

21. The apparatus of claim 20 wherein the fixed voltage node is ground.

22. The apparatus of claim 1 further including a first bypass switch coupled between the input and the first output.

23. The apparatus of claim 22 further including a second bypass switch coupled between the input and the second output.

24. The apparatus of claim 23 wherein the first bypass switch and the second bypass switch are solid state switches.

25. The apparatus of claim 1 wherein the switch matrix comprises solid state switches.

26. The apparatus of claim 25 wherein the solid state switches are field effect transistors (FETs).

27. The apparatus of claim 1 wherein the switch matrix comprises micro-electromechanical systems (MEMS) contact switches.

28. The apparatus of claim 1 further comprising a first regulator circuit having a first reference voltage input, a first unregulated input coupled to the first output of the switch matrix, and a first regulated output, wherein a first feedback loop coupled between the first regulated output and the first reference voltage input is configured to maintain a first regulated voltage at the first regulated output that is proportional to a first reference voltage at the first reference voltage input.

29. The apparatus of claim 28 further comprising a second regulator circuit having a second reference voltage input, a second unregulated input coupled to the second output of the switch matrix, and a second regulated output, wherein a second feedback loop coupled between the second regulated output and the second reference voltage input is configured to maintain a second regulated voltage at the second regulated output that is proportional to a second reference voltage at the second reference voltage input.

30. The apparatus of claim 1 wherein the first desired output voltage is equal to (1−

X)·

V_S wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4, and the second desired output voltage is equal to (1+X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, and 2/3 in a second buck/boost mode.

31. The apparatus of claim 1 wherein the first desired output voltage is equal to (1+X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, and 2/3, and the second desired output voltage is equal to X·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4 in a second boost/buck mode.

32. The apparatus of claim 1 wherein the first desired output voltage is equal to (1+X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, and 2/3, and the second desired output voltage is equal to (1−

X)·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4 in a second boost/buck mode.

33. The apparatus of claim 22 wherein the first desired output voltage is equal to V_S and the second desired output voltage is equal to X·

V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4.

34. The apparatus of claim 23 wherein the first desired output voltage is equal to X·

V_S and the second desired output voltage is equal to V_S, wherein X is one of 1/4, 1/3, 1/2, 2/3, and 3/4.