Timing device having multi-purpose pin with proactive function

• US 9,954,516 B1
• Filed: 08/19/2015
• Issued: 04/24/2018
• Est. Priority Date: 08/19/2015
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Li, Hui, Ng, Teck Chuan
• Primary Examiner(s): Shin, Jeffrey
• Application Number:
  US14/830,698
• Time in Patent Office: 979 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

A timing device that includes an OTP NVM, a first periodic signal generator operable to generate a periodic signal having a first frequency, a second periodic signal generator operable to generate a periodic signal having a frequency that is lower than the first frequency, and selection logic. In a first operating mode, the selection logic is configured to output the first periodic signal at an output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal when the crystal clock feedback signal is not received at the input terminal. In a second operating mode, the selection logic is configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.

Claims

1. A timing device comprising:

an input terminal;

an output terminal;

a data storage device configured to store one or more operating mode selection bit; and

a first periodic signal generator operable to generate a first periodic signal having a first frequency at an output thereof;

a second periodic signal generator operable to generate a second periodic signal having a second frequency at an output thereof, the second frequency lower than the first frequency; and

selection logic electrically coupled to the input terminal, the output terminal, the data storage device, the first periodic signal generator and the second periodic signal generator, the selection logic configured to receive the one or more operating mode selection bit from the data storage device, and when the configuration data indicates a first operating mode the selection logic configured to output the first periodic signal at the output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal at the output terminal when the crystal clock feedback signal is not received at the input terminal, and when the one or more operating mode selection bit indicates a second operating mode the selection logic configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.

2. The timing device of claim 1 wherein the selection logic further comprises:

a clock selection circuit operable to select either the first periodic signal or the second periodic signal as output based on the one or more operating mode selection bit and the input received at the input terminal; and

an output disable circuit operable to disable the output at the output terminal based on the one or more operating mode selection bit and the input received at the input terminal.

3. The timing device of claim 1 wherein the duty cycle of the second periodic signal is less than the duty cycle of the first periodic signal.

4. The timing device of claim 3 wherein the second periodic signal has a duty cycle that is less than 50%.

5. The timing device of claim 1 wherein the first periodic signal generator comprises a crystal oscillator circuit configured to be electrically coupled to a piezoelectric crystal and a phase locked loop (PLL) circuit electrically coupled to the crystal oscillator circuit and operable for generating the first periodic signal.

6. The timing device of claim 5 further comprising at least one frequency divider electrically coupled to receive an input clock signal and operable to divide the input clock signal to generate the first clock signal.

7. The timing device of claim 1 wherein the date storage device comprises a one time programmable non volatile memory (OTP NVM) operable to receive configuration data that includes the one or more operating mode selection bit and operable to burn the configuration data into the OTP NVM so as to store the one or more operating mode selection bit in the OTP NVM.

8. The timing device of claim 7 wherein the OTP NVM, the selection logic, the first periodic signal generator and the second periodic signal generator are formed on a single semiconductor die.

9. The timing device of claim 1 wherein the second frequency is between 1 KHz and 40 KHz.

10. The timing device of claim 1 wherein the timing device is configured to be electrically coupled to an integrated circuit device having a crystal driver input terminal and a crystal driver output terminal to provide an output clock signal that corresponds to the output clock signal generated by a piezoelectric crystal, and is also configured to be electrically coupled to an integrated circuit device having a clock terminal configured to receive a conventional clock signal, the timing device not including an additional input terminal configured to receive a Power_Down signal.

11. The timing device of claim 1 wherein the date storage device comprises a one time programmable non volatile memory (OTP NVM) operable to receive configuration data and operable to burn the configuration data into the OTP NVM so as to store configuration data in the OTP NVM that includes the one or more operating mode selection bit, wherein the input terminal is operable in a OTP NVM burn mode to receive a high voltage signal for burning the configuration data into the OTP NVM.

12. A clock distribution system, comprising:

a first integrated circuit device selected from the group consisting of an integrated circuit device having a crystal driver input terminal and crystal driver output terminal, and an integrated circuit device having a clock input terminal and not having a crystal driver output terminal; and

a timing device comprising;

an input terminal;

an output terminal;

a one time programmable non volatile memory (OTP NVM) operable to receive configuration data including one or more operating mode selection bit and operable to burn the configuration data into the OTP NVM so as to store the configuration data in the OTP NVM;

a first periodic signal generator operable to generate a first periodic signal having a first frequency at an output thereof;

a second periodic signal generator operable to generate a second periodic signal having a second frequency at an output thereof, the second frequency lower than the first frequency and the duty cycle of the second periodic signal lower than the duty cycle of the first periodic signal;

selection logic electrically coupled to the input terminal, the output terminal, the OTP NVM, the first periodic signal generator and the second periodic signal generator, the selection logic configured to receive configuration data read from the OTP NVM, and when the first integrated circuit device is an integrated circuit device having a crystal driver input terminal and a crystal driver output terminal, the output terminal is electrically coupled to the crystal driver input terminal and the input terminal is electrically coupled to the crystal driver output terminal, and when the configuration data indicates a first operating mode the selection logic configured to output the first periodic signal at an output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal when the crystal clock feedback signal is not received at the input terminal; and

wherein, when the first integrated circuit device is an integrated circuit device having a clock input terminal and not having a crystal driver output terminal, the output terminal is electrically coupled to the clock input terminal and the input terminal is electrically coupled to receive an output enable signal, and when the configuration data indicates a second operating mode the selection logic configured to output at the output terminal the first periodic signal as long as an output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.

13. The timing device of claim 12 wherein the first periodic signal generator comprises a crystal oscillator circuit configured to be electrically coupled to a piezoelectric crystal and a phase locked loop (PLL) circuit electrically coupled to the crystal oscillator circuit and operable for generating the first periodic signal.

14. The timing device of claim 12 further comprising at least one frequency divider electrically coupled to receive an input clock signal and operable to divide the input clock signal to generate the first clock signal.

15. The timing device of claim 12 wherein the OTP NVM, the selection logic, the first periodic signal generator and the second periodic signal generator are formed on a single semiconductor die.

16. A method for controlling operation of a timing device comprising:

storing in the timing device one or more bit indicating an operating mode;

when the configuration data indicates a first operating mode outputting a first periodic signal having a first frequency at an output terminal as long as a crystal clock feedback signal is received at an input terminal and outputting a second periodic signal having a second frequency that is less than the first frequency when the crystal clock feedback signal is not received at the input terminal; and

when the configuration data indicates a second operating mode outputting the first periodic signal as long as a output enable signal is received at the input terminal and not providing any output at the output terminal when the output enable signal is not received at the input terminal.

17. The method of claim 16 wherein the configuration data comprises a single bit that indicates one of the first operating mode or the second operating mode.

18. The method of claim 16 wherein the configuration data indicates the first operating mode, the method further comprising coupling the timing device to an integrated circuit device having a crystal driver input terminal and crystal driver output terminal.

19. The method of claim 17 wherein the configuration data indicates the second operating mode, the method further comprising:

coupling the timing device to a first integrated circuit device having a clock input terminal and not having a crystal driver output terminal; and

coupling the timing device to a second integrated circuit device operable to generate the output enable signal.

20. The method of claim 16 wherein the storing in the timing device one or more bit indicating an operating mode further comprises:

receiving at the timing device configuration data including the one or more bit indicating an operating mode; and

burning the configuration data into a one time programmable non volatile memory (OTP NVM.