Bulk acoustic wave resonator based fractional frequency synthesizer and method of use

• US 9,954,541 B1
• Filed: 03/29/2016
• Issued: 04/24/2018
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Goyal, Pankaj, Aycock, Stephen E.
• Primary Examiner(s): Kinkead, Arnold
• Application Number:
  US15/084,067
• Time in Patent Office: 756 Days
• Field of Search: 331 2, 331 16, 331 17, 331 34, 331107 A, 331 18
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/326 the resonator being an acoustic wave device, e.g. SAW or BAW device
• CPC Class Codes: H03B 5/366 and comprising means for varying the frequency by a variable voltage or current
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A frequency synthesizer comprising a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit outputting a first tuned frequency signal and a first plurality of integer divider circuits coupled to receive the first tuned frequency signal from the first PLL circuit and each of the first plurality of integer-only post-PLL divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer.

Claims

1. A frequency synthesizer comprising:

a first phase locked loop (PLL) circuit, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit coupled to receive a reference frequency signal from a reference oscillator and to output a first tuned frequency signal; and

a first plurality of integer divider circuits coupled to receive the first tuned frequency signal of the first PLL circuit, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer wherein a ratio of the frequency tuning range of the BAW resonator to a center frequency of the BAW resonator is a minimum ratio for the plurality of output frequency signals.

2. The frequency synthesizer of claim 1, wherein the first PLL circuit further comprises:

a first phase detector having a first input coupled to receive the reference frequency signal and a second input coupled to receive a first feedback signal from the first fractional feedback divider circuit; and

a first loop filter coupled to receive a first difference signal from the first phase detector and to output a first control signal to the first VCO.

3. A frequency synthesizer comprising:

a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator and to output a first tuned frequency signal, the first PLL circuit including a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator, a first fractional feedback divider circuit, and a tuning circuit that includes a cross-coupled transistor pair, a first capacitor bank coupled to the source nodes of the cross-coupled transistor pair and a second capacitor bank coupled to the drain nodes of the cross-coupled transistor pair; and

a first plurality of integer divider circuits coupled to receive the first tuned frequency signal, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer.

4. The frequency synthesizer of claim 3, wherein the cross-coupled transistor pair are N-type metal-oxide-semiconductor (NMOS) transistors.

5. The frequency synthesizer of claim 3, wherein the first capacitor bank and the second capacitor bank comprise a plurality of digitally controlled tuning capacitor elements, and wherein each tuning capacitor element has a capacitance value of the order of 10⁻

15 farad.

6. A frequency synthesizer comprising:

a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator and to output a first tuned frequency signal, the first PLL circuit including a first phase detector, a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit;

a first plurality of integer divider circuits coupled to receive the first tuned frequency signal, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer; and

a second PLL circuit comprising;

a second phase detector having a first input coupled to receive the first tuned frequency signal;

a second loop filter coupled to receive a second difference signal from the second phase detector and to output a control signal;

a second voltage controlled oscillator (VCO) coupled to receive the control signal from the second loop filter and configured to output a second tuned frequency signal, wherein the second VCO is selected from a ring voltage controlled oscillator and an LC voltage controlled oscillator, and

a feedback divider circuit having an input coupled to receive the second tuned frequency signal and to output a second feedback signal to a second input of the second phase detector.

7. A frequency synthesizer comprising:

a reference oscillator outputting a reference frequency signal;

a first phase locked loop (PLL) circuit coupled to receive the reference frequency signal and to output a first tuned frequency signal, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit;

a first plurality of integer divider circuits coupled to receive the first tuned frequency signal, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer; and

a second phase locked loop (PLL) circuit coupled to receive the first tuned frequency signal, the second PLL circuit to output a second tuned frequency signal, wherein a loop bandwidth of the first PLL circuit is narrower than a loop bandwidth of the second PLL circuit; and

a second plurality of integer divider circuits coupled to receive the second tuned frequency signal, each of the second plurality of integer divider circuits to provide one of the plurality of output frequency signals of the frequency synthesizer.

8. A frequency synthesizer comprising:

a reference oscillator outputting a reference frequency signal;

a first phase locked loop (PLL) circuit coupled to receive the reference frequency signal and to output a first tuned frequency signal, the first PLL circuit including a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator, a first fractional feedback divider circuit, and a tuning circuit comprising;

that includes a cross-coupled transistor pair, a first capacitor bank coupled to the source nodes of the cross-coupled transistor pair and a second capacitor bank coupled to the drain nodes of the cross-coupled transistor pair;

a first plurality of integer divider circuits coupled to receive the first tuned frequency signal of the first PLL circuit, each of the first plurality of integer divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer; and

a second phase locked loop (PLL) circuit coupled to receive the first tuned frequency signal, the second PLL circuit to output a second tuned frequency signal; and

a second plurality of integer divider circuits coupled to receive the second tuned frequency signal, each of the second plurality of integer divider circuits to provide one of the plurality of output frequency signals of the frequency synthesizer.

9. A method of generating a plurality of output frequency signals, the method comprising:

receiving a reference frequency signal;

generating a first tuned BAW generated frequency signal that is fractionally related to the reference frequency signal;

dividing the first tuned BAW generated frequency signal by an integer value to generate one of the plurality of output frequency signals of the frequency synthesizer; and

wherein generating a first tuned BAW generated frequency signal further comprises selecting a BAW resonator to generate the first tuned BAW generated frequency signal wherein a ratio of the frequency tuning range of the BAW resonator to a center frequency of the BAW resonator is a minimum ratio required to generated the plurality of output frequency signals.

10. A method of generating a plurality of output frequency signals, the method comprising:

receiving a reference frequency signal;

generating a first tuned BAW generated frequency signal that is fractionally related to the reference frequency signal by adjusting a capacitance value of a first capacitor bank coupled to the source nodes of a cross-coupled transistor pair of a tuning circuit, adjusting a capacitance value of a second capacitor bank coupled to the drain nodes of the cross-coupled transistor pair of the tuning circuit; and

dividing the first tuned BAW generated frequency signal by an integer value to generate one of the plurality of output frequency signals.