Apparatus and method of performing a decimation on a signal for pattern detection

• US 9,954,633 B2
• Filed: 08/19/2015
• Issued: 04/24/2018
• Est. Priority Date: 06/18/2015
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Pralea, Radu D.
• Primary Examiner(s): Sefcheck, Gregory B
• Application Number:
  US14/830,100
• Publication Number:
  US 20160373222A1
• Time in Patent Office: 979 Days
• Field of Search: None
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04J 11/00 Orthogonal multiplex systems, e.g. using WALSH codesH04J13/00 takes precedence
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2636 with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
• CPC Class Codes: H04L 27/2663 Coarse synchronisation, e.g. by correlation
• CPC Class Codes: H04L 27/2672 Frequency domain

Abstract

The present application relates to a receiver for performing a decimation on a signal for pattern detection and a method of operating thereof. A frequency-domain decimator component and a pattern detector component arranged at the receiver are provided. The frequency-domain decimator component is coupled to at least one antenna to receive an input sequence of samples of the signal received at the at least one antenna. The frequency-domain decimator component is further configured to apply an anti-aliasing filter and to decimate the input sequence. The frequency-domain decimator component is further arranged to output the input sequence filtered and decimated as output sequence. The pattern detector component is coupled to the frequency-domain decimator component to receive the output sequence. The pattern detection component is further configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns.

Claims

1. A receiver for performing a decimation on a signal for pattern detection, said apparatus comprising:

a frequency-domain decimator component coupled to at least one antenna to receive an input sequence of samples of the signal received at the at least one antenna,

wherein the received signal comprises an access pattern,

wherein the frequency-domain decimator component is configured to apply an anti-aliasing filter and to decimate the input sequence,

wherein the frequency-domain decimator component is further arranged to output the input sequence filtered and decimated as output sequence; and

a pattern detector component coupled to the frequency-domain decimator component to receive the output sequence, wherein the pattern detection component is configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns;

wherein the frequency-domain decimator component further comprises;

a signal partitioner component arranged to partition the input sequence into a number of input blocks each having the same length and overlapping in time by a predefined number of samples;

a signal concatenator component arranged to remove a predefined number of samples overlapping from output blocks and to concatenate the remaining part of the of the output blocks to form the output sequence;

an N-point frequency-domain transform component arranged to sequentially receive the input blocks and to transform the input blocks into frequency-mapped input blocks in frequency domain; and

an L-point time-domain transform component arranged to sequentially receive frequency-mapped output blocks and to transform the frequency-mapped output blocks into output blocks in time domain.

2. The receiver according to claim 1,

wherein the frequency-domain decimator component is configured to decimate the input sequence by a predefined decimation factor,

wherein the output sequence comprises a number of samples reduced by the predefined decimation factor in relationship to the number of samples of the input sequence.

3. The receiver according to claim 1,

wherein the frequency-domain decimator component is configured to apply an overlap and save method for filtering and decimating.

4. The receiver according to claim 1, wherein the frequency-domain decimator component further comprises:

a mixer component to apply the anti-aliasing filter arranged to receive a frequency-mapped input block and to generate a spectral product block by multiplying the frequency-mapped input block and a frequency-mapped filter sequence, wherein the frequency-mapped input block and a frequency-mapped filter sequence have the same number of spectral samples.

5. The receiver according to claim 4, wherein the decimator component further comprises:

an aliasing component to decimate the input sequence arranged to partition the spectral product block into a predefined number of aliasing blocks and to coherently add the aliasing blocks to obtain an aliased block forming a frequency-mapped output block,

wherein the predefined number of aliasing blocks corresponds to a predefined decimation factor,

wherein the frequency-mapped output block comprises the number of spectral samples reduced by the predefined decimation factor in relationship to the frequency-mapped input block.

6. The receiver according to claim 4,

wherein the anti-aliasing filter is a low-pass, LP, frequency impulse response, FIR, filter,

wherein the magnitudes of the stop band of the LP FIR filter exceeds the dynamic range defined by the numerical value representation in the frequency domain.

7. The receiver according to claim 6,

wherein the stop band of the LP FIR filter attenuates the spectral samples of the frequency-mapped input blocks below the minimum representable value defined by the numerical value representation used for the spectral samples of the frequency-mapped input blocks,

wherein the mixer component is further arranged to omit the multiplying of spectral samples at the stop band frequencies, which spectral samples are attenuated below the minimum representable value, and to set the spectral samples of the spectral product block at the stop band frequencies to zero values.

8. The receiver according to claim 7,

wherein the aliasing component is further configured to disregard aliasing blocks comprising zero value spectral samples.

9. The receiver according to claim 1,

wherein the predefined patterns for pattern detection are based on a cyclic shifted Zadoff-Chu root sequence.

10. A method of performing a decimation on a signal for pattern detection, said method comprising:

receiving an input sequence of samples of the signal received at least one antenna, wherein the received signal comprises an access pattern;

applying an anti-abasing filter in frequency domain on the input sequence;

decimating the input sequence in frequency domain by a frequency-domain decimator component to generate a filtered and decimated input sequence forming an output sequence;

performing a pattern detection based on cross-correlation valises in frequency domain between the output sequence and predefined patterns by a pattern detector component;

partitioning the input sequence into a number of input blocks each having the same length and overlapping in time by a predefined number of samples;

removing a predefined number of samples overlapping in time from each output blocks and concatenating the remaining parts, of the of the output blocks (zn) to form the output sequence;

sequentially receiving the input blocks and transforming the input blocks into frequency-mapped input blocks in frequency domain by an N-point frequency-domain transform component; and

sequentially receiving frequency-mapped output blocks and transforming the frequency-mapped output blocks into output blocks in time domain by an L-point time-domain transform component.

11. The method according to claim 10,

wherein the decimating in frequency domain comprises decimating the input sequence by a predefined decimation factor,

wherein the output sequence comprises a number of samples reduced by the predefined decimation factor in relationship to the number of samples of the input sequence.

12. The method according to claim 10, further comprising:

applying the anti-aliasing filter by multiplying each frequency-mapped input block and a frequency-mapped filter sequence to generate spectral product blocks, wherein the frequency-mapped input blocks and the frequency-mapped filter sequence have the same number of spectral samples.

13. The method according to claim 12,

wherein the decimating further comprises partitioning each spectral product block into a predefined number of aliasing blocks and coherently adding the aliasing blocks to obtain an abased block forming a frequency-mapped output block,

wherein the predefined number of aliasing blocks corresponds to the predefined decimation factor,

wherein each frequency-mapped output block comprises the number of spectral samples reduced by the predefined decimation factor in relationship to the frequency-mapped input block.

14. The method according to claim 12, further comprising:

providing a low-pass, LP, frequency impulse response, FIR, filter as the anti-abasing filter, the magnitudes of the stop band of which exceed the dynamic range defined by the numerical value representation in the frequency domain.

15. The method according to claim 12, further comprising:

omitting the multiplying of spectral samples at the stop band frequencies, which spectral samples are attenuated below the minimum representable value; and

setting the spectral samples of the spectral product block at the stop band frequencies to zero values.

16. A non-transitory, tangible computer readable storage medium bearing computer executable instructions of performing a decimation on a signal for pattern detection, wherein the instructions, when executing on one or more processing devices, cause the one or more processing devices to perform a method comprising:

receiving an input sequence of samples of the signal received at at least one antenna,

wherein the received signal comprises an access pattern;

applying an anti-aliasing filter in frequency domain on the input sequence;

decimating the input sequence in frequency domain by a frequency-domain decimator component to generate a filtered and decimated input sequence forming an output sequence;

perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns by a pattern detector component;

partition the input sequence into a number of input blocks each having the same length and overlapping in time by a predefined number of samples;

remove a predefined number of samples overlapping in time from each output blocks and concatenating the remaining parts of the of the output blocks (zn) to form the output sequence;

sequentially receive the input blocks and transforming the input blocks into frequency-mapped input blocks in frequency domain by an N-point frequency-domain transform component; and

sequentially receive frequency-mapped output blocks and transforming the frequency-mapped output blocks into output blocks in time domain by an L-point time-domain transform component.

17. A receiver for performing a decimation on a signal for pattern detection, said apparatus comprising:

a frequency-domain decimator component coupled to at least one antenna to receive an input sequence of samples of the signal received at the at least one antenna,

wherein the received signal comprises en access pattern,

wherein the frequency-domain decimator component is configured to apply an anti-aliasing filter and, to decimate the input sequence,

wherein the frequency-domain decimator component is further arranged to output the input sequence filtered and decimated as output sequence; and

a pattern detector component coupled to the frequency-domain decimator component to receive the output sequence, wherein the pattern detection component is configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns;

wherein the frequency-domain decimator component further comprises;

a mixer component to apply the anti-aliasing filter arranged to receive a frequency-mapped input block and to generate a spectral product block by multiplying the frequency-mapped input block and a frequency-mapped filter sequence, wherein the frequency-mapped input block and a frequency-mapped filter sequence have the same number of spectral samples;

wherein the anti-aliasing filter is a low-pass, LP, frequency impulse response, FIR, filter,

wherein the magnitudes of the stop band of the LP FIR filter exceeds the dynamic range defined by the numerical value representation in the frequency domain.