Minimum height CMOS image sensor

• US 9,955,099 B2
• Filed: 06/21/2016
• Issued: 04/24/2018
• Est. Priority Date: 06/21/2016
• Status: Active Grant

• Current Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Original Assignee: Hand Held Products Incorporated (Honeywell International Inc.)
• Inventors: Feng, Chen, Bremer, Edward C., Xian, Tao, Giordano, Patrick Anthony, Kearney, Sean Philip, Poloniewicz, Paul
• Primary Examiner(s): SELBY, GEVELL V
• Application Number:
  US15/187,845
• Publication Number:
  US 20170366774A1
• Time in Patent Office: 672 Days
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/42 by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

A CMOS image sensor for a camera assembly is provided, having a sensor die with opposing faces, an upper face, and a lower face. On the upper face, the sensor die is provided with a sensor array, an analog-to-digital conversion module, a digital logic circuit, and a timing and clock control circuit. The sensor array is substantially centered on the sensor die. The analog-to-digital conversion module is split into two submodules. Each submodule is disposed adjacent to the sensor array and positioned on opposing sides of the sensor array. The digital logic circuit forms a first row. The timing and clock control circuit and the analog signal processing circuit are adjacent and form a second row. The first and second rows have similar dimensions and are disposed on opposite sides of the sensor array.

Claims

1. A CMOS image sensor for a camera assembly comprising:

a sensor die having opposing faces, an upper face and a lower face;

the sensor die having components on the upper face comprising;

a sensor array having a first set and a second set of opposing sides;

the first set being a top edge and a bottom edge, the second set being a first edge and a second edge, the sensor array being substantially centered on the sensor die;

an analog-to-digital conversion module;

the analog-to-digital conversion module being disposed in two submodules, each submodule disposed adjacent to the sensor array and positioned on opposing sides of the sensor array selected from the first set and the second set;

a digital logic circuit forming a first row;

a timing and clock control circuit;

an analog signal processing circuit;

the timing and clock control circuit and the analog signal processing circuit being adjacent and forming a second row; and

the first row and the second row having similar dimensions and being disposed on opposite sides of the second set of opposing sides.

2. The CMOS image sensor of claim 1, wherein the analog-to-digital conversion submodules are split evenly dimensionally.

3. The CMOS image sensor of claim 2, wherein each analog-to-digital conversion submodule form a submodule row positioned adjacent each of the second set of opposing sides, one submodule row being intermediate the sensor array first edge and the first row, and the second submodule row being intermediate the sensor array second edge and the second row.

4. The CMOS image sensor of claim 2, wherein each analog-to-digital conversion submodule form a submodule column positioned adjacent each of the first set of opposing sides.

5. The CMOS image sensor of claim 1, further comprising a memory die, the memory die being provided with a frame buffer memory, the memory die having opposing first and second faces;

the memory die and the sensor die having substantially similar face dimensions;

the first face of the memory die being under, dimensionally aligned to, and adjacent to the lower face of the sensor die;

the CMOS image sensor further comprising through silicon vias, the through silicon vias electrically connecting the memory die and the sensor die.

6. The CMOS image sensor of claim 5, further comprising a processing die, the processing die having an upper face;

the processing die and the memory die having substantially similar face dimensions;

the upper face of the processing die being under, dimensionally aligned to, and adjacent to the second face of the memory die;

the processing die and the memory die being electrically connected with through silicon vias.

7. The CMOS image sensor of claim 1, wherein the sensor die has opposing vertical edges parallel to the second set of opposing sides of the sensor array;

the CMOS image sensor further comprising bonding pads, the bonding pads forming two bonding pad rows, the first bonding pad row being positioned on the upper face of the sensor die contiguous to one of the opposing vertical edges of the sensor die, the second bonding pad row being positioned on the upper face of the sensor die contiguous to the second of the opposing vertical edges of the sensor die.

8. The CMOS image sensor of claim 5, further comprising a processing die having a central processing unit;

the processing die being on the memory die.

9. The CMOS image sensor of claim 6, wherein the processing die includes a central processing unit.

10. The CMOS image sensor of claim 1, wherein the sensor array is a pixel sensor color imaging array consisting of pixels arranged in rows and columns;

and wherein the sensor array has an output sequence for the pixels captured on the sensor array to the analog-to-digital conversion module;

the output sequence configured to send pixels to the analog-to-digital conversion module column-by-column, even numbered pixels in a column going to one of the analog-to-digital conversion submodules to be converted into digital output, and odd numbered pixels in a column going to the other of the analog-to-digital conversion submodules to be converted into digital output;

the digital output from the two analog-to-digital conversion submodules being recombined at an output port of the sensor die.

11. The CMOS image sensor of claim 10, further comprising a video sequence converter, the video sequence converter being disposed on the lower face of the sensor die;

the video sequence converter having a dual port frame buffer, digital logic, and timing control;

the video sequence converter being configured to receive the digital output from the two analog-to-digital conversion submodules in column-by-column image format;

the video sequence converter being further configured to output digital images in row-by-row image format.

12. The CMOS image sensor of claim 11, wherein the video sequence converter frame buffer includes digital read out logic to correct geometric distortion.

13. The CMOS image sensor of claim 11, wherein the video sequence converter is configured to output digital images in even and odd rows separately to support interlace display.

14. The CMOS image sensor of claim 10, further comprising a video sequence converter, the video sequence having a dual port frame buffer, digital logic, and timing control;

the video sequence converter being configured to receive the digital output from the two analog-to-digital conversion submodules in column-by-column image format;

the video sequence converter being further configured to output digital images in row-by-row image format;

the video sequence converter being disposed at a location other than on the sensor die, the location being selected from a die electrically connected with through silicon vias to the sensor die.

15. A CMOS image sensor for a camera assembly comprising:

a sensor die having opposing faces, an upper face and a lower face, the sensor die having opposing vertical edges;

the sensor die having components on the upper face comprising;

a sensor array having a first set and a second set of opposing sides;

the first set being a top edge and a bottom edge, the first set being parallel to the opposing vertical edges of the sensor die, the second set being a first edge and a second edge, the sensor array being substantially centered between the opposing vertical edges on the sensor die;

an analog-to-digital conversion module;

the analog-to-digital conversion module being disposed adjacent to the sensor array and positioned in a row between one of the vertical edges of the sensor die and one of the second set of opposing sides of the sensor array;

a digital logic circuit forming a first row;

a timing and clock control circuit;

an analog signal processing circuit;

the timing and clock control circuit and the analog signal processing circuit being adjacent and forming a second row; and

the first row and the second row having similar dimensions, the first and second row being disposed on opposite sides of the second set of opposing sides.

16. The CMOS image sensor of claim 15, further comprising a memory die, the memory die having first and second opposing faces;

the memory die and the sensor die having substantially similar face dimensions;

the first face of the memory die being under, dimensionally aligned to, and adjacent to the lower face of the sensor die;

the CMOS image sensor further comprising through silicon vias, the through silicon vias electrically connecting the memory die and the sensor die.

17. The CMOS image sensor of claim 16, further comprising a processing die, the processing die having an upper face;

the processing die and the memory die having substantially similar face dimensions;

the upper face of the processing die being under, dimensionally aligned to, and adjacent to the second face of the memory die;

the processing die and the memory die being electrically connected with through silicon vias.

18. The CMOS image sensor of claim 15, further comprising bonding pads, the bonding pads forming two bonding pad rows, the first bonding pad row being positioned on the upper face of the sensor die contiguous to one of the opposing vertical edges of the sensor die, the second bonding pad row being positioned on the upper face of the sensor die contiguous to the second of the opposing vertical edges of the sensor die.

19. The CMOS image sensor of claim 16, wherein the memory die includes a frame buffer memory.

20. The CMOS image sensor of claim 17, wherein the processing die includes a central processing unit.