Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value

• US 9,958,341 B2
• Filed: 09/23/2017
• Issued: 05/01/2018
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Jagan, Mirellys
• Application Number:
  US15/713,643
• Publication Number:
  US 20180010968A1
• Time in Patent Office: 220 Days
• Field of Search: 374170, 374100, 374163, 374178
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

Claims

1. A method of operating a semiconductor device, comprising:

in response to a power supply voltage transitioning to at least a first potential, setting a temperature range of a temperature window to a first range by operation of a temperature circuit formed on the semiconductor device; and

in response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.

2. The method of claim 1, further including:

changing the temperature range of the temperature window includes incrementing a count value by operation of a counter circuit.

3. The method of claim 1, wherein:

after the temperature of the semiconductor device is within the temperature window, outputting performance parameter values from a performance parameter table to operational circuits based on the temperature range of the temperature window;

wherein

the operation of the operational circuits is modified by the performance parameter values.

4. The method of claim 1, wherein:

the semiconductor device comprises a dynamic random access memory device.

5. The method of claim 4, wherein:

the temperature window is stored on the semiconductor device as a multi-bit value having at least 4 binary bits.

6. The method of claim 5, wherein:

the multi-bit value has at least 5 binary bits.

7. The method of claim 1, wherein:

the semiconductor device is configured to set the temperature window to any of a plurality of temperature ranges in which the semiconductor device can operate.

8. The method of claim 7, wherein:

the first range is about midway between the highest and lowest of the plurality of temperature ranges.

9. The method of claim 7, wherein:

at least one of the temperature ranges overlaps a portion of another of the temperature ranges.

10. The method of claim 9, wherein:

the temperature ranges include a highest temperature range, a lowest temperature range, and a plurality of intermediate temperature ranges, each intermediate temperature range overlapping a portion of an adjacent temperature range.

11. A method of operating a semiconductor device, comprising:

in response to at least one predetermined condition of the semiconductor device, establishing a first temperature window for the semiconductor device by operation of a temperature circuit formed on the semiconductor device; and

in response to a temperature of the semiconductor device being determined to be outside of the first temperature window, by operation of the temperature circuit, establishing a second temperature window that is determined to include the temperature of the semiconductor device;

wherein

the first temperature window corresponds to a first temperature range, the second temperature window corresponds to a second temperature range, the first and second temperature ranges being separated by a plurality of temperature ranges.

12. The method of claim 11, wherein:

the at least one predetermined condition includes a power supply voltage of the semiconductor device transitioning from at least a first potential to a second potential.

13. The method of claim 11, wherein:

the semiconductor device is configured to operate in any one of a plurality of temperature windows, including a highest temperature window and a lowest temperature window; and

the first temperature window is between the highest and lowest temperature windows.

14. The method of claim 11, wherein:

the semiconductor device is configured to operate in any one of a plurality of temperature windows and includes a table storing performance values for at least some of the temperature windows; and

in response to establishing the second temperature window, outputting performance parameters from the table corresponding to the second temperature window to operational circuits;

wherein

the operation of the operational circuits is modified by the performance parameter values.

15. The method of claim 11, wherein:

the semiconductor device is a semiconductor memory device.

16. The method of claim 11, wherein:

the semiconductor device is a processor.

17. The method of claim 11, wherein:

the semiconductor device is a dynamic random access memory device; and

establishing the first temperature window includes setting a multi-bit window value of at least 4 binary bits to an initial value.

18. The method of claim 17, wherein:

the multi-bit window value includes at least 5 binary bits.

19. The method of claim 17, wherein:

establishing the second temperature window by changing the multi-bit window value in response to a detected temperature of the semiconductor device.

20. The method of claim 19, wherein:

changing the multi-bit window value includes incrementing or decrementing the multi-bit window value.