Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program

• US 9,958,495 B2
• Filed: 12/04/2015
• Issued: 05/01/2018
• Est. Priority Date: 12/05/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cheon, Young Hoe, Hwang, Chan Seok
• Primary Examiner(s): AISAKA, BRYCE M
• Application Number:
  US14/959,178
• Publication Number:
  US 20160161546A1
• Time in Patent Office: 879 Days
• Field of Search: 716115
• CPC Class Codes: G01R 31/2646 for measuring noise G01R31/2616, G01R31/2626 take precedence
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Claims

1. A computing device that includes a memory storing a program and a processor that executes the program, wherein, when executed by the processor, the program performs a process for analyzing power noise in a semiconductor device, where the semiconductor device includes a transistor model and a power network modeled according to a power network model, the process comprising:

obtaining first current information of a current in the transistor model before an analysis is performed on the current in the transistor model, without using an ideal supply voltage condition and based on an assumption that the power network model exists;

performing a first operation on the first current information and a power network matrix that represents an electrical characteristic of the power network model, to generate a first analysis result at a first time;

obtaining second current information of the current in the transistor model after generating the first analysis result, using the ideal supply voltage condition and based on an assumption that the power network model does not exist, and using the first analysis result;

modifying the second current information, at a second time after the first time, to generate a second analysis result comprising second modified current information; and

analyzing power noise for the semiconductor device for a period including from the first time to the second time by performing a second operation on the second analysis result and the power network matrix to generate a power noise analysis,

wherein the semiconductor device is fabricated based on a result of the analyzing power noise, and

wherein the second modified current information is generated by performing a third operation on the second current information, the first analysis result, and parameters of the transistor model, and

the first analysis result is a result of reflecting power noise when the power network model is connected to the transistor model.

2. The computing device of claim 1, wherein the process further comprises:

generating the power network matrix based on power network information.

3. The computing device of claim 1, wherein the second modified current information is derived based on a rate between the second modified current information and the second current information when the transistor model is in a saturation region.

4. The computing device of claim 1,

wherein the first analysis result and the power noise analysis result are voltage vectors associated with at least one node connected to the transistor model and the power network model.

5. The computing device of claim 4, wherein the voltage vectors are calculated using a linear analysis.

6. The computing device of claim 1, wherein the process further comprises:

obtaining third current information of the current in the transistor model after generating the second analysis result, using the ideal supply voltage condition and based on the assumption that the power network model does not exist, and using the second analysis result;

modifying the third current information, at a third time after the second time, to generate a third analysis result comprising third modified current information; and

analyzing power noise for the semiconductor device for a period including from the second time to the third time by performing a fourth operation on the third analysis result and the power network matrix to generate a power noise analysis.

7. The computing device of claim 1,

wherein the process performed by the program when executed by the processor further includes:

modifying structures of the power network model in the semiconductor device based on detecting a drop in voltage used to drive cells of the semiconductor device.

8. A computer-readable storage medium that stores a program which, when executed by a processor, performs a process for analyzing power noise in a semiconductor device modeled according to a power network model and a transistor model, the process comprising:

obtaining first current information of a current in the transistor model before an analysis is performed on the current in the transistor model, without using an ideal supply voltage condition and based on an assumption that the power network model exists;

performing a first operation on the first current information and a power network matrix that represents an electrical characteristic of the power network model, to generate a first analysis result at a first time;

obtaining second current information of the current in the transistor model after generating the first analysis result, using the ideal supply voltage condition and based on an assumption that the power network model does not exist, and using the first analysis result;

modifying the second current information, at a second time after the first time, to generate a second analysis result comprising second modified current information; and

analyzing power noise for the semiconductor device for a period including from the first time to the second time by performing a second operation on the second analysis result and the power network matrix to generate a power noise analysis,

wherein the semiconductor device is fabricated based on a result of the analyzing power noise, and

wherein the second modified current information is generated by performing a third operation on the second current information, the first analysis result, and parameters of the transistor model, and

the first analysis result is a result of reflecting power noise when the power network model is connected to the transistor model.

9. The computer-readable medium of claim 8, wherein the process further comprises generating the power network matrix based on power network information.

10. The computer-readable medium of claim 8, wherein the process further comprises:

obtaining third current information of the current in the transistor model after generating the second analysis result, using the ideal supply voltage condition and based on the assumption that the power network model does not exist, and using the second analysis result;

modifying the third current information, at a third time after the second time, to generate a third analysis result comprising third modified current information; and

analyzing power noise for the semiconductor device for a period including from the second time to the third time by performing a fourth operation on the third analysis result and the power network matrix to generate a power noise analysis.

11. The computer-readable medium of claim 8,

wherein the process performed by the program when executed by the processor further includes:

modifying structures of the power network model in the semiconductor device based on detecting a drop in voltage used to drive cells of the semiconductor device.