Data processing device and method of conducting a logic test in a data processing device

• US 9,959,172 B2
• Filed: 11/25/2013
• Issued: 05/01/2018
• Est. Priority Date: 11/25/2013
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: McLaughlin, Steven, Devine, Alan, Gorman, Alistair James, Roberston, Alistair Paul
• Primary Examiner(s): Kudirka, Joseph R
• Application Number:
  US15/035,017
• Publication Number:
  US 20160275008A1
• Time in Patent Office: 1,618 Days
• Field of Search: 713 1, 713 2, 714 30, 714 31
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics.

A method of operating a data processing device is also described.

Claims

1. A data processing device, comprising a processing unit and a test control unit connected to the processing unit, wherein the processing unit and the test control unit are arranged to:

in response to a normal boot signal, perform a normal boot action which comprises normal booting of the processing unit;

start a logic test of the processing unit;

detect a test abort event;

in response to the test abort event, perform an event response action which comprises aborting the logic test and dedicated booting of the processing unit,

wherein said dedicated booting includes executing an event handling routine and said normal booting of the processing unit does not include executing the event handling routine.

2. The data processing device of claim 1, wherein said event response action further comprises, after said operating the processing unit executing the event handling routine:

rebooting the processing unit without executing the event handling routine.

3. The data processing device of claim 1, wherein said normal booting comprises fully initializing the data processing device and wherein said dedicated booting comprises initializing the data processing device only partially.

4. The data processing device of claim 1, wherein the processing unit has a reset vector and said event response action comprises:

setting the reset vector to an address of the event handling routine.

5. The data processing device of claim 1, wherein said test control unit comprises triple-voting stateful elements.

6. The data processing device of claim 1, comprising an input unit connected or connectable to the test control unit, wherein the test abort event comprises a transition at the input unit.

7. The data processing device of claim 6, wherein the processing unit has a run mode and a low power mode.

8. The data processing device of claim 7, arranged to conduct said logic test with the processing unit operating in the run mode.

9. The data processing device of claim 7, comprising a wake-up unit connected or connectable to the input unit, wherein the wake-up unit is arranged to wake the processing unit up in response to a wake-up event when the processing unit is in the low power mode.

10. The data processing device of claim 1, arranged to reboot in response to completing the logic test, without executing the event handling routine.

11. The data processing device of claim 1, wherein the test control unit is arranged to generate an error signal in response to detecting that a period of predefined length has passed without completing a logic test of the processing unit.

12. The data processing device of claim 1, wherein the processing unit comprises one or more processor cores.

13. The data processing device of claim 1, implemented as a system-on-chip.

14. A method of operating a data processing device, the data processing device comprising a processing unit, wherein the method comprises:

in response to a normal boot signal, performing a normal boot action which comprises normal booting of the processing unit;

starting a logic test of the processing unit;

detecting a test abort event;

in response to the test abort event, performing an event response action which comprises aborting the logic test and which further comprises dedicated booting of the processing unit,

wherein said dedicated booting of the processing unit includes executing an event handling routine and said normal booting of the processing unit does not include executing the event handling routine.

15. The method of claim 14, wherein said event response action further comprises, after said operating the processing unit executing the event handling routine:

rebooting the processing unit without executing the event handling routine.

16. The method of claim 14, wherein said normal booting comprises fully initializing the data processing device and wherein said dedicated booting comprises initializing the data processing device only partially.

17. The method of claim 14, wherein the processing unit has a reset vector and said event response action comprises:

setting the reset vector to an address of the event handling routine.

18. The method of claim 14, wherein said test control unit comprises triple-voting stateful elements.

19. The method of claim 14, comprising an input unit-connected or connectable to the test control unit, wherein the test abort event comprises a transition at the input unit.