Offset-printing method for three-dimensional printed memory

• US 9,959,910 B2
• Filed: 12/07/2016
• Issued: 05/01/2018
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Bashar, Mohammed A
• Application Number:
  US15/371,235
• Publication Number:
  US 20170084621A1
• Time in Patent Office: 510 Days
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10B 20/10 : ROM devices comprising bipolar components
• CPC Class Codes: H10B 20/25 : One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM

Abstract

The present invention discloses an offset-printing method for a three-dimensional printed memory. The mask-patterns for different memory levels are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different memory levels.

Claims

1. An offset-printing method for printing at least two data-coding layers in a three-dimensional printed memory with a data-mask, comprising the steps of:

1) forming a substrate circuit on a semiconductor wafer, wherein said wafer comprises at least two adjacent dice including first and second dice;

2) forming a first memory level above said substrate circuit, including a first printing step for transferring a first mask pattern to a first data-coding layer in said first memory level, wherein an origin of said data-mask is initially aligned to an origin of said first dice at said first printing step;

3) forming a second memory level above said first memory level, including a second printing step for transferring a second mask pattern to a second data-coding layer in said second memory level, wherein said origin of said data-mask is initially aligned to an origin of said second dice at said second printing step;

wherein said first and second mask patterns are located on said data-mask.

2. The method according to claim 1, wherein said data-mask comprises at least first and second mask-regions whose mask patterns are transferred to said first and second data-coding layers.

3. The method according to claim 2, wherein the mask pattern of said first mask-region is transferred to said first data-coding layer in said first dice at said first printing step.

4. The method according to claim 2, wherein the mask pattern of said second mask-region is transferred to said first data-coding layer in said second dice at said first printing step.

5. The method according to claim 2, wherein the mask pattern of said first mask-region is transferred to said second data-coding layer in said second dice at said second printing step.

6. The method according to claim 2, wherein the mask pattern of said second mask-region is transferred to said second data-coding layer in said first dice at said second printing step.

7. The method according to claim 2, wherein said first memory level of said first dice stores a first data-array.

8. The method according to claim 2, wherein said second memory level of said first dice stores a second data-array.

9. The method according to claim 2, wherein said first memory level of said second dice stores a second data-array.

10. The method according to claim 2, wherein said second memory level of said second dice stores a first data-array.

11. The method according to claim 1, wherein said first printing step is photo-lithography.

12. The method according to claim 1, wherein said second printing step is photo-lithography.

13. The method according to claim 1, wherein said first printing step is imprint-lithography.

14. The method according to claim 1, wherein said second printing step is imprint-lithography.