Timed sense amplifier circuits and methods in a semiconductor memory

• US 9,959,912 B2
• Filed: 02/02/2016
• Issued: 05/01/2018
• Est. Priority Date: 02/02/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Jung, Chulmin, Ahmed, Fahad, Yoon, Sei Seung, Kim, Keejong
• Primary Examiner(s): Ojha, Ajay
• Application Number:
  US15/013,897
• Publication Number:
  US 20170221551A1
• Time in Patent Office: 819 Days
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

Claims

1. A memory, comprising:

a memory cell;

at least one bitline coupled to the memory cell;

a sense amplifier coupled to the at least one bitline;

a timing circuit configured to enable the sense amplifier during a read operation;

a control circuit configured to enable the sense amplifier independent of the timing circuit for an extended time period longer than a period for the read operation and determine whether the sense amplifier changes states during the extended enabling period; and

a pull-up circuit configured to pull up the at least one bitline while the sense amplifier is enabled by the control circuit.

2. The memory of claim 1, wherein the extended time period is based on a signal external to the memory.

3. The memory of claim 1, further comprising a dummy bitline circuit configured to match an electrical characteristic of the at least one bitline, wherein the timing circuit is further configured to enable the sense amplifier in response to the dummy bitline circuit.

4. The memory of claim 1, wherein the pull-up circuit comprises a precharge circuit configured to precharge the at least one bitline for the read operation.

5. The memory of claim 4, wherein the control circuit is further configured to decouple a read precharge signal from the precharge circuit to enable the pull-up circuit to pull up the at least one bitline while the sense amplifier is enabled by the control circuit.

6. The memory of claim 1, further comprising

a wordline coupled to the memory cell;

and

an address decoder configured to assert the wordline for the read operation while the sense amplifier is enabled by the control circuit.

7. The memory of claim 6, further comprising

a plurality of memory cells comprising the memory cell;

and

a plurality of wordlines comprising the wordline respectively coupled to the plurality of memory cells,

wherein the address decoder is further configured to assert the plurality of wordlines while the sense amplifier is enabled by the control circuit.

8. The memory of claim 1, further comprising a voltage adjustment circuit configured to set the sense amplifier to a predetermined state during the enabling of the sense amplifier.

9. The memory of claim 1, wherein the control circuit is further configured to detect a sense amplifier failure that occurred while the sense amplifier is enabled by the control circuit.

10. The memory of claim 1, wherein the at least one bitline comprises a pair of differential bitlines, and the pull-up circuit is configured to pull up each of the pair of differential bitlines while the sense amplifier is enabled by the control circuit.

11. A method for operating a memory, comprising:

enabling a sense amplifier in a read operation by a timing circuit, the sense amplifier being coupled to at least one bitline, and the at least one bitline being coupled to a memory cell;

enabling the sense amplifier for an extended time period longer than a period for the read operation independent of the timing circuit in a second operation;

pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation; and

determining whether the sense amplifier changes states during the extended enabling period.

12. The method of claim 11, wherein the extended time period is based on a signal external to the memory.

13. The method of claim 11, wherein the timing circuit comprises a dummy bitline circuit configured to match an electrical characteristic of the at least one bitline.

14. The method of claim 11, further comprising precharging the at least one bitline for the read operation by the pull-up circuit.

15. The method of claim 14, wherein the pulling up the at least one bitline by the pull-up circuit while the sense amplifier is enabled in the second operation comprises decoupling a read precharge signal from the pull-up circuit.

16. The method of claim 11, further comprising asserting a wordline coupled to the memory cell for the read operation and for the second operation.

17. The method of claim 16, further comprising asserting a plurality of wordlines, comprising the wordline, respectively coupled to a plurality of memory cells, comprising the memory cell, while the sense amplifier is enabled for the second operation.

18. The method of claim 11, further comprising setting the sense amplifier to a predetermined state during the enabling of the sense amplifier for the second operation.

19. The method of claim 11, further comprising detecting a sense amplifier failure that occurred while the sense amplifier is enabled for the second operation.

20. The method of claim 11, wherein the at least one bitline comprises a pair of differential bitlines;

further comprising pulling up each of the pair of differential bitlines while the sense amplifier is enabled for the second operation.

21. A memory, comprising:

a plurality of memory cells;

a plurality of wordlines respectively coupled to the plurality of memory cells;

at least one bitline coupled to one memory cell of the plurality of memory cells;

a sense amplifier coupled to the at least one bitline;

a control circuit configured to enable the sense amplifier for an extended time period longer than a period for a read operation and determine whether the sense amplifier changes states during the extended enabling period; and

an address decoder configured to assert the plurality of wordlines while the sense amplifier is enabled by the control circuit.

22. The memory of claim 21, further comprising a pull-up circuit configured to pull up the at least one bitline while the sense amplifier is enabled by the control circuit.

23. The memory of claim 22, wherein the at least one bitline comprises a pair of differential bitlines, and the pull-up circuit is configured to pull up each of the pair of differential bitlines while the sense amplifier is enabled by the control circuit.

24. The memory of claim 21, wherein the extended time period is based on a signal external to the memory.

25. The memory of claim 21, wherein the control circuit is further configured to enable the sense amplifier in a non-read operation.

26. The memory of claim 25, further comprising a timing circuit configured to enable the sense amplifier during a read operation, wherein the control circuit is configured to enable the sense amplifier independent of the timing circuit.

27. The memory of claim 25, further comprising a pull-up circuit configured to pull up the at least one bitline while the sense amplifier is enabled by the control circuit in the non-read operation and configured to precharge the at least one bitline for a read operation.

28. The memory of claim 27, wherein the control circuit is further configured to decouple a read precharge signal from the pull-up circuit while the sense amplifier is enabled by the control circuit in the non-read operation.

29. The memory of claim 21, wherein the control circuit is further configured to detect a sense amplifier failure that occurred while the sense amplifier is enabled by the control circuit.

30. An apparatus, comprising:

a plurality of memory cells;

a plurality of wordlines respectively coupled to the plurality of memory cells;

at least one bitline coupled to one memory cell of the plurality of memory cells;

sense amplifying means for sensing data on the at least one bitline;

timing means for enabling the sense amplifier means during a read operation;

control means for enabling the sense amplifying means independent of the timing circuit means for an extended time period longer than a period for the read operation and determine whether the sense amplifier changes states during the extended enabling period; and

address decoding means for asserting the plurality of wordlines.